Block Preview

Introduction

Detailed documentation for this block is not available yet.

Pin Description

START Input 1 bit BIT
CLK Input 1 bit BIT
Default: Default Board Clock
SYNC TRIG IN Input 1 bit BIT
SYNC RESET IN Input 1 bit BIT
SYNC CLK IN Input 1 bit BIT
BUSY Output 1 bit BIT
FIFO_FULL Output 1 bit BIT
RUN Output 1 bit BIT

Properties

Property window

Name EndpointName

Name of the endpoint the software uses to reach this packet. Edited in the packet designer.

Default: CP_0

Number of samples per channel Samples

Depth of the output FIFO in 32 bit words. Edited in the packet designer.

Default: 1024

Options: 128 256 512 1024 2048 4096 8192 16384 32768 65536 131072 262144 524288

Packet Layout PacketLayout

Packet layout, in the same JSON schema the 1.x editor wrote. Double-click the block to edit it.

SIM. Output SimOutput

What the block writes to disk WHEN THE PROJECT IS SIMULATED (no effect on the synthesized design). None: nothing is written, and no simulation code is generated at all. Single file: every packet built goes into one file, one after the other. Multi file per packet: one file per packet. The files are written in the sim_results folder of the project, named after _.

Default: None

Options: None Single file Multi file per packet

SIM. Data Format SimDataFormat

How the packet words are written. Binary - little endian (default): raw byte stream, 4 bytes per 32-bit word, least significant byte first. Binary - big endian: the same, most significant byte first. Hex text: one row per packet, ‘<time_ns> …’.

Default: Binary - little endian

Options: Binary - little endian Binary - big endian Hex text

SIM. Max Packets SimMaxPackets

Stop capturing after this many packets. 0 means no limit.

Default: 1024