Xilinx
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Introduction

This block implements a FIFO buffer for data transfer between asynchronous clock domains. Write and read operations use independent clocks (CLK_WR, CLK_RD) and can occur at different rates.

Key features:

  • Asynchronous read/write clocks
  • FULL and EMPTY status flags
  • Programmable almost-full/almost-empty thresholds
  • Overflow and underrun detection

Pin Description

IN Input Variable bit BIT VECTOR
Input data to write. Width: Bit Width (1-1024).
Default: Must be connected
WR Input 1 bit BIT
Write enable (1-bit). Writes IN to FIFO on CLK_WR rising edge when not FULL.
Default: Must be connected
RD Input 1 bit BIT
Read enable (1-bit). Reads data from FIFO on CLK_RD rising edge when not EMPTY.
Default: Must be connected
CLK_RD Input 1 bit BIT
Read clock. Independent from CLK_WR.
Default: Must be connected
CLK_WR Input 1 bit BIT
Write clock. Independent from CLK_RD.
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset. Resets pointers to empty state.
Default: Must be connected
OUT Output Variable bit BIT VECTOR
Output data from read. Width: Bit Width. Valid 1 cycle after RD=1.
EMPTY Output 1 bit BIT
Empty flag (1-bit). HIGH when FIFO has no data to read.
FULL Output 1 bit BIT
Full flag (1-bit). HIGH when FIFO has no space to write.
PROG_EMPTY Output 1 bit BIT
Programmable empty flag (1-bit). HIGH when data count ≤ Prog Empty threshold.
PROG_FULL Output 1 bit BIT
Programmable full flag (1-bit). HIGH when data count ≥ Prog Full threshold.
OVERFLOW Output 1 bit BIT
Overflow flag (1-bit). HIGH when write attempted while FULL.
UNDERRUN Output 1 bit BIT
Underrun flag (1-bit). HIGH when read attempted while EMPTY.

Properties

Property window

FIFO depth MemorySize

Set the amount of memory in number of words

FIFO depth in words. Allowed: 64-65536. Total storage = FIFO depth × Bit Width.

Default: 1024

Options: 64 128 256 512 1024 2048 4096 8192 16384 32756 65536

Bit Width BusWidth

Set the size in bits of the data

Bit width per word. Range: 1-1024.

Default: 16

Range: 1 – 1024

Prog Empty ProgEmpty

Set PROG_EMPTY threshold in word. MUST BE BETWEEN 3 AND FIFO SIZE -3!

Programmable empty threshold (3 to FIFO size-3). PROG_EMPTY asserts when count ≤ this value.

Default: 3

Range: 3 – 65535

Prog Full ProgFull

Set PROG_FULL threshold in word. MUST BE AT MAXIMUM FIFO SIZE - 3!

Programmable full threshold (1 to FIFO size-3). PROG_FULL asserts when count ≥ this value.

Default: 1021

Range: 1 – 65535

Functional description

FIFO maintains read and write pointers:

  • Write: When WR=1 and not FULL, data is written on CLK_WR edge
  • Read: When RD=1 and not EMPTY, data is read on CLK_RD edge

Status flags

  • EMPTY: No data available to read
  • FULL: No space available to write
  • PROG_EMPTY: Data count below Prog Empty threshold
  • PROG_FULL: Data count above Prog Full threshold
  • OVERFLOW: Write attempted when FULL
  • UNDERRUN: Read attempted when EMPTY

Timing

Read latency: 1 clock cycle (data appears 1 CLK_RD cycle after RD=1).

Typical use cases

  • Clock domain crossing
  • Rate matching between fast producer and slow consumer
  • Data buffering in streaming systems