Xilinx
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Introduction

Violet noise rises at +6 dB per octave ($f^2$ PSD) – the spectrum of differentiated white noise, useful to stress high-frequency behavior (e.g. emulating the noise floor shape after an analog differentiator or testing HF rejection). The block computes $v[n] = (x[n] - x[n-1])/2$ on the embedded white source.

Violet noise PSD

Measured on the bit-exact model the hardware is verified against; the dashed line is the ideal +6 dB/octave slope.

Pin Description

CE Input 1 bit BIT
Clock enable: one new sample per clock where high. Default: ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Clears the difference register and restarts from the seed.
Default: Default Board Reset
OUT Output 16 bit BIT VECTOR
Violet noise sample, signed, OutputBits wide.
DV_OUT Output 1 bit BIT
High on every clock carrying a new sample.

Properties

Property window

Output bits OutputBits

Width of the OUT word (2..32), signed.

Output width (2..32), signed.

Default: 16

Range: 2 – 32

SEED (32 digit hex) SEED

Seed of the embedded white generator (128 bit hex), expanded internally with SplitMix64. Auto-randomized when the component is created, so multiple instances produce independent noise; editable for reproducible runs. RESET restarts the sequence. Violet noise, +6 dB/octave (first difference of white noise).

128-bit seed of the embedded white generator, 32 hexadecimal digits (auto-randomized at placement, editable for reproducible runs). Every string of exactly 32 hex digits is a valid seed - repeated digits, all zeros and two identical 64-bit halves included; a wrong length or a non-hex digit is a compile error. Two seeds that differ at all give two independent noise streams (guaranteed when they differ in one 64-bit half, which includes any single-digit difference), which is what makes several instances of this block decorrelated. NOTE: the seed expansion was corrected in this version, so the same seed produces a different (equally reproducible) stream than in earlier releases.

Default: A3887512C91B4EE28A47951B41B4106B

Usage

One sample per CE clock, one clock latency. CE defaults to ‘1’.