Chronometer (Start/Stop)
Synchronous chronometer with explicit start and stop controls. Measures elapsed time (in clock cycles) between START and STOP events. Provides precise control over measurement intervals with optional automatic reset on overflow. Configurable counter width from 8 to 64 bits.
Introduction
This block measures elapsed time between explicit START and STOP events by counting clock cycles. It provides precise control over measurement intervals using edge-triggered start/stop signals.
Operation modes:
- START pulse: Rising edge initiates counting
- STOP pulse: Rising edge halts counting
- Repeated measurements: Can restart after stop for consecutive measurements
The chronometer provides three outputs:
- TIME - Current elapsed time count (in clock cycles)
- RUNNING - Indicates when chronometer is actively counting
- OVERFLOW - Pulses high when counter wraps around
$$ \mathrm{TIME}(n+1) = \begin{cases} 0 & \text{if START edge detected} \ \mathrm{TIME}(n) + 1 & \text{if RUNNING=‘1’ and CE=‘1’} \ \mathrm{TIME}(n) & \text{otherwise} \end{cases} $$
Pin Description
Start trigger input (rising edge triggered).
Rising edge initiates a new measurement:
- Resets TIME to 0
- Sets RUNNING=‘1’
- Begins counting
Pulse must be at least 1 clock cycle wide. Subsequent rising edges while RUNNING=‘1’ restart the measurement.
Stop trigger input (rising edge triggered).
Rising edge halts the measurement:
- Clears RUNNING=‘0’
- Freezes TIME at current value
- Stops counting
Pulse must be at least 1 clock cycle wide. Has no effect if RUNNING=‘0’.
Automatic reset control (active high).
- ‘1’ = Counter automatically resets to 0 after overflow
- ‘0’ = Counter wraps to 0 on overflow without reset
Applies during active counting (RUNNING=‘1’). Independent of START/STOP behavior.
Clock enable input (active high).
Global clock enable for the counter. When CE=‘0’, counting is suspended regardless of RUNNING state.
Typically tied to ‘1’ for normal operation.
Default: Connects to ‘1’ if left unconnected.
Clock input.
Counter increments on rising edge when RUNNING=‘1’ and CE=‘1’. START and STOP edges are also sampled on rising CLK edge.
Default: Connects to global clock if left unconnected.
Synchronous reset input (active high).
- ‘1’ = Reset counter to 0, clear RUNNING flag
- ‘0’ = Normal operation
Master reset independent of START/STOP.
Default: Connects to global reset if left unconnected.
Running status output.
- ‘1’ = Chronometer is actively counting (between START and STOP)
- ‘0’ = Chronometer is idle (waiting for START or after STOP)
This is a registered output. Transitions:
- ‘0’ → ‘1’ on START rising edge
- ‘1’ → ‘0’ on STOP rising edge or RESET
Overflow flag output (single-cycle pulse).
Pulses high for one clock cycle when counter reaches maximum value (2^N - 1) and wraps to 0.
Only occurs while RUNNING=‘1’. Indicates measurement exceeded counter capacity.
Current time count output (unsigned integer).
Contains the accumulated clock cycle count since last START event. Width is configurable via the Bit Number property.
Behavior:
- Resets to 0 on START rising edge
- Increments while RUNNING=‘1’ and CE=‘1’
- Holds value when RUNNING=‘0’
- Wraps/resets on overflow (based on AUTORESET)
To convert to real time: Time (seconds) = TIME / CLK_Frequency (Hz)
Properties
Set the number of bit used in the timer accumulator
Number of bits in the time counter.
Available values: 8, 16, 24, 32, 40, 48, 56, 64
Determines maximum measurable time:
- Max count = 2^BitNumber - 1
- Max time = (2^BitNumber - 1) / CLK_Frequency
Example: 32-bit @ 100 MHz = 42.9 seconds max
Choose based on expected maximum interval between START and STOP. If measurements exceed this range, OVERFLOW will pulse.
Default: 32
Options: 8 16 24 32 40 48 56 64
Functional description
The chronometer implements a state machine with START/STOP control:
State machine behavior
IDLE State (RUNNING=‘0’):
- Waiting for START pulse
- TIME holds previous measurement
- Rising edge on START → transition to COUNTING state
COUNTING State (RUNNING=‘1’):
- TIME increments every clock cycle (when CE=‘1’)
- Rising edge on STOP → transition to IDLE state
- Counter continues until STOP received
Edge detection
Both START and STOP inputs are edge-triggered:
- Only rising edges are recognized
- Pulse width doesn’t matter (minimum 1 clock cycle)
- Simultaneous START and STOP: START takes priority
Time calculation
To convert TIME count to real time:
$$ \text{Elapsed Time (seconds)} = \frac{\mathrm{TIME}}{\text{CLK Frequency (Hz)}} $$
Overflow behavior
When counter reaches maximum value (2^N - 1):
- AUTORESET=‘1’: Counter resets to 0, continues counting
- AUTORESET=‘0’: Counter wraps to 0, continues counting
- OVERFLOW: Pulses high for one clock cycle
Timing diagram
The diagram shows:
- START rising edge initiates counting (TIME resets to 0)
- Counter increments while RUNNING=‘1’
- STOP rising edge halts counting
- TIME retains final value until next START
- Second START begins new measurement
Typical use cases
- Event-to-event timing: Measure time between two specific events
- Pulse width measurement: START on rising edge, STOP on falling edge
- Trigger-to-response timing: Measure system response time
- Execution profiling: START at function entry, STOP at exit
- Data acquisition timing: Measure time between acquisition triggers
- Protocol timing: Measure inter-packet gaps or transmission times
Design considerations
START/STOP signal requirements
- Minimum pulse width: 1 clock cycle
- Edge type: Rising edge only
- Glitch filtering: Input signals should be clean (consider adding synchronizers for async signals)
- Priority: If START and STOP occur simultaneously, START takes priority
Choosing bit width
Select counter width based on maximum expected measurement time:
| Bit Width | Max Count | @ 100 MHz | @ 200 MHz |
|---|---|---|---|
| 8 bits | 255 | 2.55 µs | 1.28 µs |
| 16 bits | 65,535 | 655 µs | 328 µs |
| 24 bits | 16,777,215 | 168 ms | 84 ms |
| 32 bits | 4,294,967,295 | 42.9 s | 21.5 s |
| 64 bits | 2^64 - 1 | ~5,849 years | ~2,925 years |
Measurement accuracy
- Resolution: 1 clock period (10 ns @ 100 MHz)
- Latency: START/STOP edges registered on next rising CLK edge
- Jitter: ±1 clock cycle due to synchronization
Using AUTORESET
- AUTORESET=‘0’: Overflow wraps counter, useful for long-running measurements
- AUTORESET=‘1’: Overflow resets counter, useful for detecting overrun conditions
- Monitor OVERFLOW output to detect if measurement exceeded counter range
Comparison with Enable-based chronometer
| Feature | Start/Stop | Enable |
|---|---|---|
| Control | Edge-triggered | Level-triggered |
| Start measurement | START rising edge | ENABLE=‘1’ |
| Stop measurement | STOP rising edge | ENABLE=‘0’ |
| Reset behavior | Auto-reset on START | Continuous accumulation |
| Best for | Event-to-event timing | Duty cycle measurement |