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Introduction

Runtime-configurable version of Convolution point (1 MAC, fixed kernel):

  • kernel coefficients are written into an internal RAM through COEF_ADDR / COEF_DATA / COEF_LOAD (one-clock pulse per write);
  • the computed point comes from the POINT input pin, latched at the START rising edge - so the point can change on every trigger.

$$ y[\text{POINT}] = \sum_{m=0}^{K-1} x[m] \cdot h[\text{POINT}-m] $$

Pin Description

IN Input InputSize bit BIT VECTOR
Signed input samples. Consumed one per clock during RUN.
Default: Must be connected
START Input 1 bit BIT
Trigger, rising-edge sensitive. Also latches POINT. Ignored while BUSY=1.
Default: Must be connected
POINT Input ceil(log2(2K-1)) bit BIT VECTOR
Convolution point to compute (0 .. 2K-2). Sampled at the START edge.
Default: Must be connected
COEF_ADDR Input ceil(log2(K)) bit BIT VECTOR
Coefficient write address (tap index 0..K-1).
COEF_DATA Input CoefSize bit BIT VECTOR
Coefficient write data (signed).
COEF_LOAD Input 1 bit BIT
One-clock pulse: latches COEF_DATA into ram[COEF_ADDR].
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
OUT Output InputSize+CoefSize+ceil(log2(K)) bit BIT VECTOR
The computed convolution point. Signed. Updated on DV.
DV Output 1 bit BIT
One-clock pulse when the result is ready.
BUSY Output 1 bit BIT
High while the K samples are being consumed.

Properties

Property window

Input Bit Width InputSize

Bit width of the signed input samples.

Bit width of the signed input samples: 16, 24 or 32.

Default: 16

Options: 16 24 32

Coefficient Bit Width CoefSize

Bit width of each kernel coefficient (signed). Width of the COEF_DATA input.

Bit width of each kernel coefficient (signed), 8..32. Width of COEF_DATA.

Default: 16

Options: 8 10 12 14 16 18 20 24 28 32

Kernel Length KernelLen

Number of kernel coefficients K (coefficient RAM depth). The IP consumes K samples after START. POINT selects the computed convolution point (0 .. 2K-2).

Number of kernel coefficients K (2..4096) = coefficient RAM depth.

Default: 64

Range: 2 – 4096

Loading the kernel

text 
  for k in 0 .. K-1:
    COEF_ADDR <= k
    COEF_DATA <= h[k]
    COEF_LOAD <= 1 for one clock

Writes are honoured on every clock, in any state; for a coherent result avoid rewriting taps while BUSY = 1.

Selecting the point

Drive POINT with the desired index (0 .. 2K-2) before raising START: the value is sampled once at the START edge, so it can be driven from a register and changed between triggers with no glitches.

Timing and width

RUN lasts K clocks (one sample per clock); DV pulses one clock after the last sample. Output width:

$$ \text{OUT_BITS} = \text{InputSize} + \text{CoefSize} + \lceil \log_2 K \rceil $$