Float 1/X TM
Time-multiplexed reciprocal operator for IEEE 754 floating-point numbers based on Xilinx Floating Point IP. Computes 1/x with single (32-bit) or double (64-bit) precision, configurable DSP usage, and multiple TM phases (1-32) for high-throughput parallel computation in digital signal processing pipelines.
Introduction
This block computes the reciprocal (multiplicative inverse) of IEEE 754 floating-point values using the Xilinx Floating Point IP core. The component supports Time Multiplexing (TM): multiple parallel computation units share the same clock cycle.
On every rising edge of CLK, if DIN_VLD = 1 and DOUT_RDY = 1:
$$ \mathrm{DOUT}(n) = \frac{1}{\mathrm{DIN}(n)} $$
Pin Description
Properties
Time Multiplexing factor (number of phases)
Number of TM phases (1 – 32).Default: 4
Range: 1 – 32
Select between single precision 32 bit and double precision 64 bit
Single or Double precision.Default: Single
Options: Single Double
DSP Usage. Single precision: No [0], Full[8]. Double precision: No[0], Full[14]
No_UsageorFull_UsageSingle: 0/8 DSPs; Double: 0/14 DSPs
Default: Full_Usage
Options: No_Usage Full_Usage
Functional description
Wraps Xilinx Floating Point IP (operation type: Reciprocal) with N parallel
instances for TM support.
Mathematical background
Reciprocal function:
$$ y = \frac{1}{x} = x^{-1} $$
Special cases:
- $\frac{1}{1} = 1$
- $\frac{1}{\infty} = 0$
- $\frac{1}{0} = \infty$
- $\frac{1}{-x} = -\frac{1}{x}$
Properties:
- $\frac{1}{1/x} = x$
- $\frac{1}{xy} = \frac{1}{x} \cdot \frac{1}{y}$
Timing
Fixed latency of 30 clock cycles per phase.
| Property | Latency (cycles) |
|---|---|
| Reciprocal | 30 |
DSP Usage
- Single precision: No [0], Full[8]
- Double precision: No[0], Full[14]
Typical use cases
- Division replacement (faster than general division)
- Normalization
- Gain inversion
- Impedance calculations
- Newton-Raphson iterations