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Introduction

The Periodic Pulse block is the simplest possible rate generator: give it a period in clock cycles and it raises PULSE for exactly one clock every time that many cycles have elapsed.

      PERIOD = 5

    CLK    _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_
    PULSE  ________________|‾|________________|‾|___
                           ^                  ^
                           5 clocks           5 clocks

It is not the same block as Pulse Generator (PWM): that one takes a period and a width and is meant for duty-cycle control. This one only ever produces a single-clock tick, which is what you want to drive a counter, an acquisition trigger, a GET request, or any “do something every N clocks” input.

Pin Description

CLK Input 1 bit BIT
System clock. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous reset, active high. Clears the counter, so the next pulse comes a full period after the reset is released.
Default: Default Board Reset
EN Input 1 bit BIT
Enable. Low freezes the counter and holds PULSE low; high resumes the interval from where it stopped. Tied to ‘1’ when left unconnected.
PULSE Output 1 bit BIT
One-clock-wide pulse, high for exactly one clock every PERIOD clocks.
PERIOD 32 bit
Period in clock cycles, unsigned. Only present when Period Source is PORT. Latched at each wrap, so a change takes effect from the next pulse. Values 0 and 1 both mean “pulse every clock”.

Properties

Property window

Period Source PeriodSource

CONSTANT: the period is the value typed below and is fixed in the bitstream. PORT: a 32-bit PERIOD input pin appears on the block and the period can be changed at run time.

  • CONSTANT – the period is fixed at compile time to the Period value below; no PERIOD pin is created.
  • PORT – a 32-bit PERIOD input pin is created and the period can be changed while the design runs.

Default: CONSTANT

Options: CONSTANT PORT

Period (clocks) Period

Number of clock cycles between two pulses, 1 to 4294967295. Only used when Period Source is CONSTANT. A period of 1 pulses every clock.

Number of clock cycles between two pulses, 1 to 4294967295, default 1000. Only used when Period Source is CONSTANT; ignored in PORT mode. Rejected when the property window is confirmed if it is not a whole number in range.

Default: 1000

Usage

Timing contract

With PERIOD = N:

  • the first pulse comes N clocks after RESET is released;
  • consecutive pulses are exactly N clocks apart;
  • PULSE is high for exactly one clock.

Where the period comes from

The Period Source property decides:

  • CONSTANT – the period is the number typed in the Period property and is fixed in the bitstream. The block has no PERIOD pin.
  • PORT – a 32-bit PERIOD input pin appears on the block and the period can be changed at run time, for example from a register.

Either way the value is a plain count of clock cycles, from 1 to 4294967295.

Changing the period at run time

The value on PERIOD is latched at each wrap, so the interval already in progress always completes with the value it started with. A new value therefore takes effect from the next pulse onwards. This is deliberate: a mid-period change can never produce a runt interval or a stretched one.

Degenerate values

PERIOD = 1 pulses on every clock. PERIOD = 0 is treated the same way: a period of zero samples has no meaning, and clamping it to 1 also keeps the internal PERIOD-1 arithmetic from wrapping around. To stop the block, use EN rather than a zero period.

EN

Driving EN low freezes the counter where it is and forces PULSE low. Raising it again resumes the interval from that point – it does not restart it. Leave it unconnected and it is tied to '1', so the block free-runs.

Typical applications

  • Acquisition or trigger tick at a fixed rate.
  • Driving GET on a queue-based block (for example the Random Generator) at a controlled rate.
  • Clock-enable / rate divider for a slower downstream stage.
  • Periodic refresh, watchdog kick or housekeeping strobe.

Resources & Timing

  • Latency: PULSE is registered: it appears one clock after the counter wraps

  • Throughput: one pulse every PERIOD clocks

Pure VHDL, no HLS, no DSP: one 32-bit counter, one comparator and a register for the latched period. In CONSTANT mode the comparison is against a constant, so synthesis prunes most of the period register.