DSP - BLOCK KURTOSIS TM
TM (time multiplexed) twin of Block Kurtosis: TM Factor (2..16) independent channels packed on one wide bus, each computing the normalised fourth central moment m4 / sigma^4 - tailedness: 1.0 for a square wave, 1.5 for a sine, 3.0 for Gaussian noise, far above 3 for an impulsive signal - of its own block of N = 2^EXP samples (EXP on a runtime pin, shared by every lane). PLAIN kurtosis, not excess; subtract 3.0 downstream per lane if you want the Gaussian-is-zero convention. No histogram, no second pass, no sample buffer, and NO SQUARE ROOT ANYWHERE - sigma^4 is a square, so each lane is BIT EXACT. One shared frame - one EXP, one IN_DV, one OUT_DV per block - with per-lane accumulators at II=1 and ONE serial tail serving the lanes one after the other, so the tail resources stay those of the scalar block whatever the lane count. Lane 0 sits in the LOW bits of every packed bus. Same per-lane numbers as the scalar twin, bit for bit. Optional shared BUSY / INTEGRATING / SAMPLE_COUNT status outputs.
Introduction
Per lane, over each block of N samples:
$$ \mathrm{KURT}_i = \frac{m_4}{m_2^2} = \frac{N^3 S_4 - 4N^2 S_1 S_3 + 6N S_1^2 S_2 - 3S_1^4}{\bigl(N S_2 - S_1^2\bigr)^2} ;; \text{(exact integer identity, } S_1..S_4\ \text{of lane } i\text{)} $$
This is the time multiplexed (TM) twin of the scalar Block Kurtosis block: TM Factor independent channels packed on one wide bus, each computing the kurtosis of its own block of N consecutive samples. Nothing is shared between the channels except the frame.
Per lane it is the classic “is something happening in this channel” detector: a rare pulse moves it hard, raising the gain does not move it at all - and with TM Factor channels on one bus this is the natural multi-channel activity monitor. THIS BLOCK REPORTS PLAIN KURTOSIS, NOT EXCESS KURTOSIS.
The TM contract
INis TM Factor lanes of input width bits each, lane 0 in the LOW bits (lane 0 is the oldest sample of the clock) - the same packing as every other TM block in the toolchain. Each lane is an independent channel: its own S1 / S2 / S3 / S4 accumulators, its own result.- ONE shared
EXPpin, ONEIN_DV, one frame: all lanes start and end their blocks on the same accepted clocks.BUSY,INTEGRATINGandSAMPLE_COUNTtherefore stay scalar -SAMPLE_COUNTcounts per-lane samples, which are identical in every lane by construction. - Accumulation runs at II=1 on the packed bus, one accumulator set per lane. TM Factor times the accumulator registers is the unavoidable cost of TM state - plus THREE real multipliers per lane (xx, x^2x and x^2*x^2) in the accumulation path.
- The serial post-processing is ONE shared engine set serving the lanes one after the other: the five serial products and the restoring division are each ONE stage, iterating lane by lane - not TM Factor of each. That is what keeps the tail resources of the SCALAR block, at the cost of tail latency x TM Factor.
- ONE
OUT_DVper block, after the LAST lane’s tail completes. All output lanes are staged as each lane finishes and committed together on theOUT_DVclock, so every packed output moves on that clock and no other.
N is a runtime input: the block size is $N = 2^{\mathrm{EXP}}$, EXP clamped to Max Block Exponent and latched on the first accepted sample of a block, so a change takes effect on the NEXT block - for every lane at once. Because N is a power of two, every N scaling in the identity is an exact shift and the N^4 factors cancel exactly - per lane.
When to use this instead of TM Factor scalar blocks
One TM block and TM Factor scalar blocks compute the same numbers. The TM block pays the per-lane accumulators (unavoidable either way) but shares ONE frame, ONE control FSM and ONE serial tail across all lanes - the more expensive the scalar tail, the more it saves, and this one’s tail is five serial products and a division. The price is tail latency (TM Factor times the scalar tail) and the coupling of the frame: all lanes must share the same block length and the same sample cadence. Channels that need different block sizes need scalar blocks.
Pin Description
IN_DV is high.
Properties
Number of INTEGER bits of the input sample (per lane) (the sign, when present, uses one of them).
Integer bits of ONE LANE of the input (the sign, when present, uses one of them). 1..64. Default 16.Default: 16
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Number of FRACTIONAL bits of the input sample (per lane), i.e. the bits to the right of the binary point. Total width = integer + fractional bits, and must not exceed 64.
Fractional bits of one lane of the input. 0..64, total lane width 2..64 bits. Default 0. They cancel exactly - the kurtosis is dimensionless.Default: 0
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Select whether the input sample (per lane) is signed (two’s complement) or unsigned.
SIGNED (two’s complement) or UNSIGNED lanes. Default SIGNED. Applies to every lane.Default: SIGNED
Options: UNSIGNED SIGNED
Number of INDEPENDENT time-multiplexed channels packed on the IN bus and on every result bus. Lane 0 occupies the LOW bits (lane 0 = the oldest sample of the clock), the same packing as every other TM block. All lanes share one EXP / IN_DV / frame; each lane gets its own accumulators, but the serial post-processing is ONE engine serving the lanes one after the other, so the tail latency (and the minimum usable EXP) grows with this factor.
Number of independent channels packed on the buses, 2..16. Default 4. Multiplies the IN width, every packed output width AND the serial tail length (the shared tail serves the lanes one after the other), so it also raises the minimum usable EXP.Default: 4
Options: 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Largest block-size exponent the accumulators are sized for: the block can be up to 2^MaxBlockExponent samples long. The EXP input is clamped to this value at run time. Raising it widens the internal accumulators, and ON THE BLOCKS WHOSE SERIAL ENGINES ARE SIZED FROM THOSE ACCUMULATORS (Coefficient of Variation, SNR, Skewness, Kurtosis, Correlation, Autocorrelation, Linear Regression) it also LENGTHENS THE SERIAL TAIL – even when the runtime EXP is small. Keep it at the largest block you actually use. The default of 20 covers blocks of up to 1048576 samples.
Largest block-size exponent the per-lane accumulators are sized for; the EXP input is clamped to it at run time. Raising it widens every lane’s S1..S4 accumulators AND lengthens the shared serial products and divider. 1..31, default 20.Default: 20
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Number of INTEGER bits of the KURTOSIS output (per lane) (the sign, when present, uses one of them).
Integer bits of ONE LANE of the KURTOSIS output. 1..64, default 10.Default: 10
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Number of FRACTIONAL bits of the KURTOSIS output (per lane), i.e. the bits to the right of the binary point. Total width = integer + fractional bits, and must not exceed 64.
Fractional bits of one lane. 0..64, default 6 (a granularity of 1/64). Each one also lengthens the shared divider by one clock per lane.Default: 6
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Select whether the KURTOSIS output (per lane) is signed (two’s complement) or unsigned.
SIGNED or UNSIGNED lanes. Default UNSIGNED (a kurtosis is non negative by construction).Default: UNSIGNED
Options: UNSIGNED SIGNED
YES: the BUSY (high from the first sample of a block until its result is out – it COVERS THE SERIAL TAIL, and its last high clock IS the OUT_DV pulse) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared BUSY pin exists. Default NO.Default: NO
Options: NO YES
YES: the INTEGRATING (high only while the block is ACCUMULATING; it drops as soon as the N-th sample has been taken and the tail starts, so BUSY-and-not-INTEGRATING means ‘computing’) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared INTEGRATING pin exists. Default NO.Default: NO
Options: NO YES
YES: the SAMPLE_COUNT (32 bit, how many samples have been accumulated so far in the current block: 1 after the first, N after the N-th. It is NOT cleared at the block end – it holds N until the NEXT block’s first accepted sample takes it back to 1. On a CONTINUOUS stream that happens DURING the serial tail, so at OUT_DV it reads how far into the next block the input has already got, NOT N. To capture the length of the block being presented, latch SAMPLE_COUNT on the clock INTEGRATING falls – that one always reads N) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared 32 bit SAMPLE_COUNT pin exists. Default NO.Default: NO
Options: NO YES
ROUND: round to nearest when a result has to be requantised into a coarser output format. TRUNCATE: drop the bits (cheaper, adds a negative bias).
ROUND / TRUNCATE at each lane’s final requantisation. Effectively a NO-OP on this block: the numerator is pre-shifted so each lane’s floored quotient already carries exactly the output resolution and nothing is left to shift. Saturation still applies. Default ROUND.Default: ROUND
Options: TRUNCATE ROUND
YES: clip to the largest representable value of each output format (symmetric for signed formats). NO: wrap around.
YES: clip each lane to its output format (symmetric for signed). NO: wrap. Default YES.Default: YES
Options: NO YES
Accuracy, per lane
Each lane is BIT EXACT, like the scalar twin: numerator and denominator are exact integers - there is NO SQUARE ROOT ANYWHERE, because sigma^4 is the SQUARE of the exact variance numerator - and the only operation on them is the floored restoring division. The harness demands tolerance 0 per lane (the golden floors identically). Being floored, each lane’s value is biased low by up to one LSB - with the default 6 fractional bits, up to 1/64; ask for more fractional bits if that matters at your threshold, and pay the divider clocks per lane.
Because each lane’s quotient already carries the output resolution, the Rounding property is effectively a NO-OP on this block (saturation still applies).
Timing: the TM latency contract
OUT_DV pulses ONCE per block, L clocks after the clock on which the
N-th sample was accepted, where
$$ L = 1 + \mathrm{TM},\bigl(8,\mathrm{IN_SW} + 7,\mathrm{EXP} + \mathrm{CNUMW}\bigr) $$
(BKUT_TAIL in the core - per lane the scalar’s serial step counts, |S1|
twice at IN_SW+e, S2 at 2IN_SW-1+e, |S1|^2 and D twice at 2IN_SW-1+2e,
plus the fixed states and the division, collapse to exactly that). This is
the family’s lane-multiplexed rule
$L_{tm}(e) = \mathrm{TM},(L_{scalar}(e)-1)+1$. The tail DEPENDS ON THE
RUNTIME EXPONENT - seven clocks per unit of EXP, per lane, the steepest in
the family. At the defaults (16 bit signed input, Q10.6 KURTOSIS, Max
Block Exponent 20, TM 4, EXP 10) CNUMW = 150, so L = 1 + 4*348 = 1393
clocks - which does NOT fit a 2^10 block: at those defaults the minimum
usable EXP is 11.
The family drop rule applies with the TM tail: the tail of one block must
finish before the NEXT block completes, $2^{{\mathrm{{EXP}}}} \ge L$, or the
completing block’s result is silently DROPPED (no OUT_DV, accumulators
unaffected, no error pin). The TM tail makes the minimum usable EXP larger
than the scalar twin’s - the compiler prints both the worst-case tail and
the minimum EXP in the compilation log, and the property window refuses a
configuration whose minimum exceeds Max Block Exponent.
Knowing where the block is: BUSY, INTEGRATING and SAMPLE_COUNT
Identical to the scalar family, and SHARED by all lanes: INTEGRATING is
high exactly while the block is accumulating (it dips one clock per block
boundary on a continuous stream), BUSY also covers the (TM-long) tail and
its last high clock IS the OUT_DV pulse, SAMPLE_COUNT reads 1 after the
first accepted sample and N after the N-th.
SAMPLE_COUNTis NOT cleared at the block end - it holds N until the NEXT block’s first accepted sample takes it back to 1. On a CONTINUOUS stream that happens DURING the serial tail (which on a TM block is TM Factor times longer), so atOUT_DVit reads how far into the next block the input has got, NOT N. The clock that always reads N is the oneINTEGRATINGfalls on - latch it there.
Verification
The core is regression tested by a host-side csim harness
(tb/block-ops-tm/run_tb_tm.ps1) with per-lane goldens computed by
gen_golden_tm.py in exact rational arithmetic ON EACH LANE’S STREAM ALONE
(lanes deliberately carry different signals - the generator refuses
identical lanes), from the TEXTBOOK central-moment definition, never from
the raw-power-sum identity the core uses - so the algebra is checked
against an independent derivation. Plus the strongest available
lane-independence check: after every run, the SCALAR twin is replayed on
each lane’s stream by itself and lane k of every TM result must match it
BIT FOR BIT. The status waveform is checked clock by clock, every packed
output is checked to move only on OUT_DV, and the TM-specific mutant
classes (shared accumulator, lane swaps, wrong-lane tail reads, early
commit, drop rule) are killed. What no host harness can prove - that Vitis
accepts and schedules the core at II=1 - is stated in AGENT/block_ops.log,
not silently implied. Note also that the DEFAULT wide formats are beyond
the host stub’s 127-bit ceiling (the tail handles 4*S1W-bit intermediates):
they are exercised only by csynth, and the harness scenarios use narrower
inputs. Said openly rather than implied away.