Xilinx
Block Preview

Introduction

The FX OFFSET block performs fixed-point addition between a data input and an offset value:

$$ \mathrm{OUT} = \mathrm{IN} + \mathrm{OFFSET} $$

Each operand (input, offset, output) has independently configurable integer and fractional bit widths. The block is particularly useful for DC offset correction, baseline subtraction, and signal centering applications.

Output includes automatic rounding (AP_RND) and saturation (AP_SAT_SYM) to handle overflow conditions gracefully.

Pin Description

IN Input Variable bit BIT VECTOR
Data input signal in fixed-point format. Width: IN Integer + IN Fraction. Arithmetic type set by IN Sign.
Default: Must be connected
IN_DV Input 1 bit BIT
Input data valid signal, active high. When high, indicates valid data on IN.
OFFSET Input Variable bit BIT VECTOR
Offset value in fixed-point format. Width: Offset Integer + Offset Fraction. Arithmetic type set by Offset Sign (default: SIGNED). Positive values shift signal up, negative values shift down.
Default: Must be connected
OUT Output Variable bit BIT VECTOR
Offset-corrected output (IN + OFFSET) in fixed-point format. Width: OUT Integer + OUT Fraction. Arithmetic type set by OUT Sign. Includes rounding and saturation.
OUT_DV Output 1 bit BIT
Output data valid signal, active high. Asserted 6 clock cycles after corresponding IN_DV.

Properties

Property window

IN Integer InBitsInt

Number of bits of the integer part of the input

Number of integer bits for input IN. Range: 0 – 128. Determines integer dynamic range.

Default: 16

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

IN Fraction InBitsFract

Number of bits of the fractional part of the input

Number of fractional bits for input IN. Range: 0 – 128. Determines fractional precision: LSB = $2^{-N}$.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

IN Sign InSign

Select if the input is signed or unsigned. Sign uses 1 bit of the integer part

Input arithmetic type:

  • UNSIGNED: ap_ufixed, range [0, $2^{N}-1$]
  • SIGNED: ap_fixed, range [$-2^{N-1}$, $2^{N-1}-1$]

Default: UNSIGNED

Options: UNSIGNED SIGNED

OUT Integer OutBitsInt

Number of bits of the integer part of the output

Number of integer bits for output OUT. Range: 0 – 128. Should accommodate max(IN_int, OFFSET_int) + 1 to avoid saturation.

Default: 16

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

OUT Fraction OutBitsFract

Number of bits of the fractional part of the output

Number of fractional bits for output OUT. Range: 0 – 128. Determines output precision after rounding.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

OUT Sign OutSing

Select if the output is signed or unsigned. Sign uses 1 bit of the integer part

Default: UNSIGNED

Options: UNSIGNED SIGNED

Offset Integer offsetBitsInt

Number of bits of the integer part of the offset

Number of integer bits for offset value. Range: 0 – 128. Default: 16 (same as input).

Default: 16

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

Offset Fraction offsetBitsFract

Number of bits of the fractional part of the offset

Number of fractional bits for offset value. Range: 0 – 128. Default: 0 (integer offset).

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

Offset Sign offsetSing

Select if the offset is signed or unsigned. Sign uses 1 bit of the integer part

Offset arithmetic type:

  • UNSIGNED: Positive offsets only
  • SIGNED: Allows both positive and negative offsets (default)

Default: SIGNED

Options: UNSIGNED SIGNED

OutSign OutSign

Output arithmetic type:

  • UNSIGNED: ap_ufixed
  • SIGNED: ap_fixed (required if input or offset is signed)

Functional description

The component adds two fixed-point numbers with configurable formats:

$$ y = x + c $$

where:

  • x → IN with format $(N_{\text{int}}, N_{\text{frac}})$
  • c → OFFSET with format $(C_{\text{int}}, C_{\text{frac}})$
  • y → OUT with format $(O_{\text{int}}, O_{\text{frac}})$

Fixed-point format

Each signal uses the ap_fixed/ap_ufixed HLS types:

  • Total width = Integer bits + Fractional bits
  • Signed/Unsigned configured independently per signal
  • Offset default: SIGNED (allows both positive and negative corrections)
  • Rounding mode: AP_RND (round to nearest)
  • Overflow mode: AP_SAT_SYM (symmetric saturation)

Data flow

The block uses a data-valid protocol:

  • IN_DV: Input data valid signal
  • OUT_DV: Output data valid signal (delayed by latency)

Latency

Fixed latency of 6 clock cycles (HLS-optimized pipeline).

Typical use cases

  • DC offset removal in signal processing
  • Baseline correction in spectroscopy
  • Signal centering before ADC
  • Pedestal subtraction in imaging