Block Preview

Introduction

The SPI Master block implements a Serial Peripheral Interface master controller for synchronous full-duplex communication with one or more slave devices.

SPI uses four main signals:

  • SCLK - Serial Clock (generated by master)
  • MOSI - Master Out, Slave In (data from master to slave)
  • MISO - Master In, Slave Out (data from slave to master)
  • CS/SS - Chip Select / Slave Select (active low)

Key features:

  • Configurable data width (1-32 bits)
  • Support for up to 16 slave devices
  • All four SPI modes supported (CPOL/CPHA combinations)
  • Continuous mode for streaming data
  • Programmable SCLK frequency

Pin Description

DATA_IN Input 8 bit BIT VECTOR
START Input 1 bit BIT
POLARITY Input 1 bit BIT
PHASE Input 1 bit BIT
ADDRESS Input 1 bit BIT
CONTINUOUS Input 1 bit BIT
MISO Input 1 bit BIT
Master In, Slave Out. Serial data input from the slave device. Connect to the slave’s data output line.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Used to generate SCLK at the configured frequency. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Default: Default Board Reset
DATA_OUT Output 8 bit BIT VECTOR
DV Output 1 bit BIT
Data Valid output, active high. Pulses high for one CLK cycle when received data is ready. Occurs on falling edge of Busy signal.
BUSY Output 1 bit BIT
MOSI Output 1 bit BIT
Master Out, Slave In. Serial data output to the slave device. Connect to the slave’s data input line.
SCLK Output 1 bit BIT
Serial Clock output. Generated clock for synchronizing data transfer. Frequency determined by CLK and SPI Speed settings.
CS 0 Output 1 each bit BIT
Chip Select output, active low. CS 0 is the first of the family: the block declares CS 0 .. CS (N-1), one per Number of Slaves, all identical apart from their index (the pad is labelled SS_0 on the block). Only the addressed select goes low, one clock before the first SCLK edge, and it stays low for the whole transfer; all of them return high together with BUSY at the end, unless Continuous mode keeps the current one asserted for back to back words. All are high while idle or in reset.
Data In Variable bit
Input data to transmit to the slave device. Width: Data Bit Size (1-32 bits). Data is latched on the rising edge of CLK when Start is high.
Default: Must be connected
Start 1 bit
Enable signal to initiate a transaction. When HIGH, latches clock settings, address, and Data In to begin transfer. Should be held high for at least one CLK cycle.
Polarity 1 bit

SPI clock polarity (CPOL).

  • 0: SCLK is normally low (idle low)
  • 1: SCLK is normally high (idle high)
Phase 1 bit

SPI clock phase (CPHA).

  • 0: Data sampled on first clock edge
  • 1: Data sampled on second clock edge
Address Variable bit
Binary address selecting the target slave device. Range: 0 to (Number of Slaves - 1). Width: ceil(log2(NumSlaves)) bits. Invalid addresses default to slave 0.
Continuous 1 bit

Continuous mode enable.

  • LOW: Complete transfer and deassert CS after data
  • HIGH: Continue with next data word without releasing CS
Reset 1 bit
Asynchronous reset, active low. When LOW, resets the SPI master to idle state. Must be HIGH for normal operation. Default: Global reset (active high, inverted internally).
Data Out Variable bit
Received data from the slave device. Width: Data Bit Size (1-32 bits). Valid when DV pulses high. Remains stable until next transfer.
Busy 1 bit

Busy/Ready status output.

  • LOW: Master is ready to accept commands
  • HIGH: Transfer in progress

Properties

Property window

Data Bit Size BitSize

Set the number of bits for data transmission (1-32)

Default: 8

Range: 1 – 32

Number of Slaves NumSlaves

Set the number of SPI slave devices (1-16)

Default: 1

Range: 1 – 16

CLK Pin Frequency (MHz) ClockFreq

Set the input clock frequency in MHz

Default: 100

Range: 1 – 500

SPI Clock Speed (KHz) SPISpeed

Set the desired SCLK frequency in KHz

Default: 1000

Range: 1 – 50000

Name Name
Instance name for this SPI Master component. Used for signal naming and identification.
DataBitSize DataBitSize

Number of bits per data word (1-32). Determines the width of Data In and Data Out ports.

Common values:

  • 8: Most common for byte-oriented devices
  • 16: 16-bit ADCs, DACs
  • 24: 24-bit ADCs
  • 32: 32-bit registers
NumberOfSlaves NumberOfSlaves

Number of slave devices (1-16). Creates one CS output for each slave.

The Address port width is automatically sized:

  • 1 slave: 1-bit address
  • 2-4 slaves: 2-bit address
  • 5-8 slaves: 3-bit address
  • 9-16 slaves: 4-bit address
CLKPinFrequency CLKPinFrequency

Frequency of the CLK input in MHz. Used to calculate the clock divider for SCLK generation.

Typical values:

  • 50 MHz: V2495 default
  • 80 MHz: DT5550 default
  • 100-200 MHz: High-speed designs
SPIClockSpeed SPIClockSpeed

Desired SCLK frequency in KHz. Must be less than half the CLK frequency.

Common SPI speeds:

  • 100-400 KHz: Slow devices, long cables
  • 1-10 MHz: Most SPI devices
  • 20-50 MHz: High-speed flash, ADCs

Actual frequency depends on CLK and may be slightly different from requested due to integer clock divider.

Functional description

The SPI Master generates the serial clock and controls data transmission with the selected slave device. Communication is full-duplex: data is simultaneously transmitted on MOSI and received on MISO.

SPI Clock Modes

The clock behavior is controlled by two parameters:

  • CPOL (Clock Polarity): Idle state of SCLK
  • CPHA (Clock Phase): Data sampling edge
Mode CPOL CPHA Description
0 0 0 SCLK idle low, sample on rising edge
1 0 1 SCLK idle low, sample on falling edge
2 1 0 SCLK idle high, sample on falling edge
3 1 1 SCLK idle high, sample on rising edge

Master and slave must be configured for the same mode.

Transaction Flow

  1. Set Data In with data to transmit
  2. Set Polarity and Phase for desired SPI mode
  3. Set Address to select target slave (0 to NumSlaves-1)
  4. Set Continuous low for single transfer, high for streaming
  5. Pulse Start high to begin transaction
  6. Busy goes high during transfer
  7. When Busy goes low, DV pulses high
  8. Read received data from Data Out

Continuous Mode

When Continuous is high during the last bit of a transfer:

  • The master latches new data from Data In
  • Transmission continues without releasing CS
  • DV pulses briefly to indicate received data is ready
  • Useful for streaming multiple words without gaps

Clock Frequency

The SCLK frequency is calculated as:

$$ f_{SCLK} = \frac{f_{CLK}}{2 \times (clk_div + 1)} $$

The compiler automatically calculates the clock divider based on the configured CLK frequency and desired SPI speed.

Timing

  • Busy asserts on the clock edge after Start is detected
  • Data is valid when Busy goes low
  • DV pulses for one clock cycle on falling edge of Busy
  • In continuous mode, DV pulses after each word transfer

Reset Behavior

The Reset input is active low (active when ‘0’):

  • All slave selects go high (deasserted)
  • MOSI goes high-impedance
  • Data Out clears to zero
  • Busy goes high during reset, low when ready