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Introduction

The Trigger Derivative core implements a derivative-based discriminator commonly used in nuclear and particle physics data-acquisition systems. The core computes the discrete derivative of the input signal and triggers when this derivative exceeds a user-defined threshold. This approach is particularly effective for detecting fast signal edges in noisy environments, where leading-edge triggers may produce false positives on slowly varying baselines.

A key feature is the programmable Pretrigger Delay, which allows the output data to be delayed relative to the trigger, enabling capture of signal samples that occurred before the trigger event.

Pin Description

DATA_IN Input WordSize bit BIT VECTOR
Input samples to be processed. Width is WordSize bits (signed representation).
Default: Must be connected
THRESHOLD Input WordSize bit BIT VECTOR
Comparator reference level V_{thr} with bit-width equal to WordSize. The derivative is compared against this threshold; a trigger occurs when derivative >= threshold.
Default: 0
INHIBIT Input 1 bit INT
Integer specifying the number of clock cycles during which new triggers are suppressed after each TRIGGER pulse (dead-time). Set to 0 for no inhibition.
Default: 0
POLARITY Input 1 bit BIT

Selects derivative polarity.

  • 1 – detect positive derivatives (rising edges)
  • 0 – detect negative derivatives (falling edges) Width = 1 bit.
Default: 1
CE Input 1 bit BIT
Clock-enable. The core processes data only when CE=1; otherwise the internal state is frozen and outputs keep their last value except TRIGGER, which is forced low.
Default: 1
CLK Input 1 bit BIT
System sampling clock. All internal operations are synchronous to the rising edge of CLK.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous active-high reset. Clears derivative history buffers, delay line, trigger state and inhibition counter.
Default: Default Board Reset
DATA_OUT Output WordSize bit BIT VECTOR
Delayed version of the input data. Width equals WordSize bits. The delay is set by the Pretrigger Delay property, allowing capture of pre-trigger samples.
DERIVATE Output WordSize bit BIT VECTOR
Computed derivative of the input signal. Width equals WordSize bits. Calculated as x[n] - x[n-d] where d is the Decorrelation parameter.
TRIGGER Output 1 bit BIT
Single-cycle pulse generated when the derivative crosses the threshold (rising edge detection). Can be used to timestamp the event or to start downstream processing.

Properties

Property window

Word Size WordSize

Set the number of bits of the data bus

Bit-width of the input and output data signals. Applies to DATA_IN, THRESHOLD, DATA_OUT and DERIVATE signals. Acceptable range: 2 … 64, default 16.

Default: 16

Range: 2 – 64

Pretrigger Delay DataDelay

Include programmable delay to embedd pretrigger logic in trigger module

Depth D of the output delay line (0 … 256). Determines the latency between DATA_IN and DATA_OUT. This parameter enables pretrigger functionality: by delaying the data output, samples acquired before the trigger event can be captured. Set to 0 for no delay (pass-through), default 0.

Default: 0

Range: 0 – 256

Decorrelation noise_filter

Set the derivative decorrelation d coefficient in the expression y = x[n] - x[n-d]

Default: 1

Range: 0 – 256

Decorrelation Decorrelation
Decorrelation delay d for the derivative computation. The derivative is computed as x[n] - x[n-d]. A value of 1 computes the standard first difference; larger values skip intermediate samples, providing noise rejection at the cost of reduced timing precision. Acceptable range: 0 … 256, default 1.

Usage

Functional overview

Let

  • x[n] be the digitised input sample at clock cycle n
  • d – Decorrelation delay (noise_filter parameter)
  • D – Pretrigger Delay (data_delay parameter)
  • V_{thr} – threshold

Derivative computation

The core computes a decorrelated derivative:

$$ \Delta x[n] ;=; x[n] - x[n-d] $$

where d is the decorrelation delay set by the Decorrelation property. A larger d value provides better noise immunity by comparing samples that are further apart in time.

Trigger decision

$$ \text{TRIGGER}[n] ;=; \begin{cases} 1 & \text{if } \Delta x[n] \ge V_{thr} \land \text{rising edge} \land \text{not inhibited} \ 0 & \text{otherwise} \end{cases} $$

The trigger is generated on the rising edge of the threshold crossing (when the derivative first exceeds the threshold after being below it). After each trigger, new triggers are inhibited for INHIBIT clock cycles.

Delay line (Pretrigger)

$$ y[n] = x[n-D] $$

where y[n] is provided on DATA_OUT and D is the pretrigger delay. This allows capturing samples that occurred before the trigger event, which is essential for waveform analysis where the signal baseline before the pulse is needed.

Note: In this example, DataDelay=2, so DATA_OUT is delayed by 2 clock cycles relative to DATA_IN.

Timing

  • The derivative is computed with a latency of 1 clock cycle from the input.
  • TRIGGER is issued 1 clock cycle after the derivative exceeds the threshold.
  • DATA_OUT is delayed by DataDelay clock cycles from DATA_IN.
  • DERIVATE output reflects the computed derivative with 1 clock cycle latency.

Typical applications

  • Fast pulse detection in scintillator/SiPM readout systems
  • Constant-fraction discriminator pre-stage
  • Edge detection in digitizer applications
  • Zero-crossing detection with noise rejection
  • Waveform capture with pretrigger samples