Float SQRT TM
Time-multiplexed square root operator for IEEE 754 floating-point numbers based on Xilinx Floating Point IP. Supports single (32-bit) and double (64-bit) precision, configurable initiation interval, and multiple TM phases (1-32) for high-throughput parallel computation in signal processing and scientific applications.
Introduction
This block computes the square root of IEEE 754 floating-point values using the Xilinx Floating Point IP core. The component supports Time Multiplexing (TM): multiple parallel computation units share the same clock cycle.
On every rising edge of CLK, if DIN_VLD = 1 and DOUT_RDY = 1:
$$ \mathrm{DOUT}(n) = \sqrt{\mathrm{DIN}(n)} $$
Pin Description
Properties
Time Multiplexing factor (number of phases)
Number of TM phases (1 – 32).Default: 4
Range: 1 – 32
Select between single precision 32 bit and double precision 64 bit
Single or Double precision.Default: Single
Options: Single Double
Number of clock cycles to execute a division. Set to 1 to perform division in realtime. Higher number reduce the area usage of the block
Initiation Interval (1 – 25). Trade-off between throughput and area.Default: 1
Range: 1 – 25
Functional description
Wraps Xilinx Floating Point IP (operation type: Square_root) with N parallel
instances for TM support.
Mathematical background
Square root function:
$$ y = \sqrt{x} $$
Properties:
- $\sqrt{0} = 0$
- $\sqrt{1} = 1$
- $\sqrt{x^2} = |x|$
- $\sqrt{xy} = \sqrt{x} \cdot \sqrt{y}$ (for $x, y \geq 0$)
- Undefined for $x < 0$ (returns NaN)
Timing
Fixed latency of 29 clock cycles per phase.
| Property | Latency (cycles) |
|---|---|
| Square Root | 29 |
Initiation Interval (II)
Range: 1 – 25 cycles. Higher values reduce area usage.
Typical use cases
- Magnitude calculations (Euclidean distance)
- RMS computation
- Standard deviation
- Complex number magnitude
- Normalization