AFE5550

Introduction link

Principle of Operation link

AFE5550 is the bulk front-door of a DT5550 design: one block, 32 output pins, each carrying the digitised samples of one analog input channel, registered on the board’s readout clock.

It is the “take everything” alternative to placing 32 individual Analog Input board pins. Both routes end up in the same place - the two share a single instance of the board’s ADC subsystem - but this block gives you the whole array in one symbol and you simply leave unwired the channels you do not care about.

   4x ADC devices ──► adcs_top ──► inversion stage ──► CH0..CH31 (16 bit @ READOUT_CLK)
                                                        │
                                     MapAFECh remap ────┤
                                                        ▼
                                            ADC_A0 .. ADC_A31 pins
  

Pin Description link

Properties link

⚙️ Detailed Operation link

The block emits nothing itself link

Component_AFE55550.CompileHDL contains no code - it returns True with an empty body. What makes the block work is one line in its constructor:

  ComponentInfo.DelegateCompile = "board_plugin"
  

The compiler (diagramc_compile.vb) sees delegate_compile = "board_plugin" in the node tag, and hands the block - designator, pad array and all - to the board plug-in’s CompileIO instead. On the DT5550 that is the If type = "AFE5550" branch of bDT5550.vb, keyed on the component’s sub-type.

The practical consequence: all the real behaviour of this block lives in the board plug-in, and a board that has no AFE5550 branch in CompileIO silently generates nothing for it.

What the board plug-in does link

1. Instantiates the ADC subsystem, once. It first tests whether the architecture text already contains the marker comment --NI ADCs istantiation; if not, it calls IstantiateAdc, which adds the ADC top-level ports, the adcs_top instance, the ADC clock constraints and the ADC_READY / ADC_STATUS signals. Because the marker is a plain string sentinel, an Analog Input block and this block share one single adcs_top - whichever is compiled first creates it.

2. Declares one signal per connected output pad (and skips the rest).

3. Remaps the channel. For each connected pad it calls MapAFECh, which translates the block pin name into the physical AFE channel that actually carries it, and emits <pad signal> <= <physical channel>;. See the pin list below for the full table - it is not the identity permutation.

4. Forces the inversion mask:

     ANALOG_INPUT_INVERSION <= x"FFFF0220";
     

   overriding the template default of x"00000000".

The inversion mask link

Inside adcs_top each channel passes a final stage clocked by READOUT_CLK:

  if inversion(n) = '0' then
    CHn <= iCHn;
else
    CHn <= x"3FFF" - iCHn;
end if;
  

The mask the board forces, x"FFFF0220", has bits 5, 9 and 16 to 31 set. Those are physical channel indices, so after the MapAFECh remap the block pins delivered inverted are ADC_A0, ADC_A1 and ADC_A16 … ADC_A31; pins ADC_A2 … ADC_A15 come through as digitised. The per-pin notes below spell this out.

Sample format link

The pins are 16 bits wide, but the inversion arithmetic subtracts from x"3FFF", which places the ADC code in the low 14 bits (0 … 16383) of the word. The exact meaning of the upper bits is not stated in these sources; treat the sample as a 14-bit unsigned code unless your own measurements say otherwise.

Timing link

• The output stage of adcs_top is registered on READOUT_CLK, which the board maps to CLK_80(0) - the 80 MHz readout clock. All 32 channels are updated on the same edge.
• There is no data-valid pin: the buses are free-running, one new sample per readout clock. Blocks that need a DV should generate it themselves (a constant '1', or a gate on ADC Ready).
• The block adds no latency of its own - it is a set of assignments.

Companion block link

The ADC_READY / ADC_STATUS signals created by the same IstantiateAdc call are what the ADC Ready block reads. Since this block is one of the two things that create them, an AFE5550 in the design is enough to make an ADC Ready block legal. Use it to hold your processing chain off until the four ADCs have finished their configuration sequence - before that, the sample buses carry whatever the untrained SERDES produces.

Board availability link

Offered only on the DT5550 (board plug-in GUID 413F904B-7FD0-43EF-B127-74278C23F1A5).

SupportedBoard also lists DT5550SE, but no board plug-in in the repository declares itself as that model, and the toolbox visibility filter in Form1_plugins.vb implements a BOARD_MODELS.DT5550 branch only. Unlike its three siblings in this plug-in, this block does not list DT5560.

Resources & Timing link

• Latency: No latency added by the block. Samples are registered once in the adcs_top output/inversion stage, on READOUT_CLK (the board maps it to CLK_80(0)).

• Throughput: 32 channels, one 16-bit sample each per readout clock, free running (no data-valid pin).

• Costs nothing by itself: the block compiles to signal declarations and concurrent assignments only, and only for the pads you actually wire.
• Shares one adcs_top instance with the Analog Input board pins; the board plug-in guards against a second instantiation with the --NI ADCs istantiation marker string.
• Creates the ADC_READY / ADC_STATUS signals that the ADC Ready block reads.