Block Preview

Introduction

This block implements non-volatile read-only memory initialized with user data during FPGA compilation. The ROM contents are fixed and cannot be modified at runtime.

Read latency: 1 clock cycle.

Pin Description

ADDR Input 16 bit BIT VECTOR
Read address (16 bits). Range: 0 to Memory Size-1. Data at this address appears on OUT after 1 clock cycle.
Default: Must be connected
CLK Input 1 bit BIT
Clock signal for read operations.
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset.
Default: Must be connected
OUT Output Variable bit BIT VECTOR
Output data. Width: Bit Width (1-1024). Latency: 1 clock cycle.

Properties

Property window

Memory Size MemorySize

Set the amount of memory in number of words

Number of words in ROM. Allowed: 4-65536. Must match data file size.

Default: 1024

Options: 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32756 65536

Bit Width BusWidth

Set the size in bits of the data

Bit width per word. Range: 1-1024 (maximum 256 in legacy docs).

Default: 16

Range: 1 – 1024

Data Format Format

Select data format as Decimal or Hexadecimal

Data format: HEX, SIGNED DECIMAL, or DECIMAL. Must match format used in RomContent file.

Default: HEX

Options: HEX SIGNED DECIMAL DECIMAL

RomContent RomContent
File content or path to .txt file with ROM data. One value per line, no “0x” prefix for hex.

Functional description

ROM stores constant data loaded from a text file:

  • Each line in the file = one memory word
  • Supports decimal or hexadecimal format
  • Data is synthesized into FPGA block RAM
  • Read-only: No write capability

Data file format

Create a .txt file with one value per line:

  A012
0012
0133
F0F1

(Example in hexadecimal format, no “0x” prefix)

Timing

Read: Apply address on ADDR; data appears on OUT 1 cycle later.

Typical use cases

  • Lookup tables (LUTs)
  • Coefficient storage for filters
  • Calibration constants
  • Waveform tables