Xilinx
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Introduction

A linear feedback shift register with the XAPP052 maximal-length tap set: for every Length $n$ from 3 to 64 the sequence walks through all $2^n - 1$ nonzero states before repeating. Every CE clock advances the register by one step (DV marks it):

  • OUT is the whole register — a PRBS word, handy as a cheap wide stimulus or address/pattern scrambler;
  • BIT is the freshly generated feedback bit — the classic serial PRBS-n bit stream (PRBS7, PRBS15, PRBS23, PRBS31 … depending on Length) used for bit-error-rate testing and link bring-up.

Being a single linear recurrence, an LFSR is spectrally flat but has a strong algebraic structure (each output bit is the same sequence delayed). When statistical quality matters, use the Uniform Random block; use this one when you want the standard PRBS sequences, the smallest possible footprint, or an exactly known period.

Seeding

  • The SEED property sets the state loaded by RESET. It is randomized automatically when the block is placed and is forced nonzero (the all-zero state would lock a XOR-feedback LFSR).
  • At runtime, drive SEED_IN with a new value and pulse LOAD for one clock: the register reloads instantly and the sequence continues from the new seed (LOAD wins over CE; DV is suppressed on the load cycle). An all-zero SEED_IN is silently replaced with 1, so the generator can never lock up. Connect the bus to a register block to re-seed from software.

The tap table is validated offline (exhaustive period check up to n = 20, algebraic maximality check for every length up to 64) and the hardware is verified against an independent Python reference: golden vectors, runtime-load semantics, zero-seed sanitization and the measured full period (255 at n = 8, 65535 at n = 16) in a self-checking GHDL regression, mutation-tested.

Pin Description

SEED_IN Input 16 bit BIT VECTOR
New seed value, Length bits. Sampled on the clock where LOAD is high. All-zero is replaced with 1 automatically.
LOAD Input 1 bit BIT
Active-high, one clock is enough: reloads the register from SEED_IN and continues from there. Has priority over CE; DV is suppressed on the load cycle. Default: ‘0’.
CE Input 1 bit BIT
Clock enable, active high: one LFSR step per clock where high. Default when unconnected: ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock. Rising edges drive all operations.
Default: Default Board Clock
RESET Input 1 bit BIT
Reloads the SEED property value: the sequence restarts identically.
Default: Default Board Reset
OUT Output 16 bit BIT VECTOR
The whole LFSR register after the step (PRBS word), Length bits.
BIT_OUT Output 1 bit BIT
The freshly generated feedback bit: the serial PRBS-Length bit stream.
DV_OUT Output 1 bit BIT
High on every clock that carries a new step (follows CE, low on load).

Properties

Property window

Length Length

LFSR register length (3..64). Maximal-length taps: the sequence repeats after 2^Length - 1 steps. Sets the width of OUT and SEED_IN.

Register length n (3..64). Maximal taps (XAPP052): period is exactly 2^n - 1. Sets the width of OUT and SEED_IN.

Default: 16

Range: 3 – 64

SEED (16 digit hex) SEED

Initial LFSR state (64-bit hex, truncated to Length bits, forced nonzero). Automatically randomized when the component is created. RESET restarts from this seed; a different seed can be loaded at runtime through SEED_IN + LOAD.

Initial state as a hex number (up to 16 digits, truncated to Length bits, forced nonzero). Auto-randomized when the component is created; editable for reproducible sequences.

Default: 5EA674A9FECC4948

Usage notes

  • Leaving CE unconnected ties it to ‘1’ (one step per clock); LOAD defaults to ‘0’.
  • The serial stream on BIT equals the LSB of OUT on every DV cycle.
  • Two instances with different seeds produce the SAME sequence at different phases (that is the nature of an LFSR): for independent streams use two different Lengths, or the Uniform Random block.
  • RESET makes runs reproducible: the sequence always restarts from the SEED property.