DSP - BLOCK COVARIANCE TM
TM (time multiplexed) twin of Block Covariance: TM Factor (2..16) independent channel PAIRS packed on TWO wide buses, each pair computing cov(a,b) = mean(a*b) - mean(a)*mean(b) over its own block of N = 2^EXP sample pairs (EXP on a runtime pin, shared by every lane). Lane k of IN_A pairs with lane k of IN_B, and ONE IN_DV qualifies both buses, so the pairing is positional per lane. One shared frame - one EXP, one IN_DV, one OUT_DV per block - with per-lane accumulators at II=1 and ONE serial tail serving the lanes one after the other, so the tail resources stay those of the scalar block whatever the lane count. Lane 0 sits in the LOW bits of every packed bus. Same per-lane numbers as the scalar twin, bit for bit. Optional shared BUSY / INTEGRATING / SAMPLE_COUNT status outputs.
Introduction
Per lane pair, over each block of N sample pairs:
$$ \mathrm{COV}_i = \frac{N\sum_k a_i[k],b_i[k] - \sum_k a_i[k] \sum_k b_i[k]}{N^2} $$
This is the time multiplexed (TM) twin of the scalar Block Covariance block: TM Factor independent channel pairs packed on two wide buses, each computing the covariance of its own block of N consecutive sample pairs. Nothing is shared between the channel pairs except the frame.
The TM contract
IN_AandIN_Bare BOTH packed TM buses: TM Factor lanes of input width bits each, lane 0 in the LOW bits of BOTH buses (lane 0 is the oldest sample of the clock) - the same packing as every other TM block in the toolchain. Lane k ofIN_Apairs with lane k ofIN_B: each lane pair is an independent two-channel covariance with its own Sa / Sb / Sab accumulators and its own result.- ONE shared
EXPpin, ONEIN_DV, one frame: the singleIN_DVqualifies EVERY lane of BOTH buses at once, so the a/b pairing is positional per lane and the two streams cannot slip inside a block - in any lane.BUSY,INTEGRATINGandSAMPLE_COUNTtherefore stay scalar -SAMPLE_COUNTcounts per-lane sample pairs, which are identical in every lane by construction. - Accumulation runs at II=1 on the packed buses, one accumulator set per lane. TM Factor times the accumulator registers is the unavoidable cost of TM state - plus one real a*b multiplier per lane in the accumulation path.
- The serial post-processing is ONE shared engine serving the lanes one after the other (the |Sa|*|Sb| shift-add product, shared, not TM Factor of it). It runs once per block, so lane-multiplexing it keeps the tail resources of the SCALAR block at the cost of tail latency x TM Factor, which is irrelevant against a whole block of samples.
- ONE
OUT_DVper block, after the LAST lane’s tail completes. All output lanes are staged as each lane finishes and committed together on theOUT_DVclock, so every packed output moves on that clock and no other.
N is a runtime input: the block size is $N = 2^{\mathrm{EXP}}$, EXP clamped to Max Block Exponent and latched on the first accepted sample of a block, so a change takes effect on the NEXT block - for every lane at once. Because N is a power of two, the division by N^2 is an exact shift in every lane.
When to use this instead of TM Factor scalar blocks
One TM block and TM Factor scalar blocks compute the same numbers. The TM block pays the per-lane accumulators (unavoidable either way) but shares ONE frame, ONE control FSM and ONE serial tail across all lanes - the more expensive the scalar tail, the more it saves. The price is tail latency (TM Factor times the scalar tail) and the coupling of the frame: all lane pairs must share the same block length and the same sample cadence. Channel pairs that need different block sizes need scalar blocks.
Pin Description
IN_B; both
are sampled together on the clocks where IN_DV is high.
IN_A.
Lane k pairs with lane k of IN_A.
Properties
Number of INTEGER bits of the input sample (per lane, both streams) (the sign, when present, uses one of them).
Integer bits of ONE LANE of both inputs (the sign, when present, uses one of them). 1..64. Default 16. IN_A and IN_B share one lane format.Default: 16
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Number of FRACTIONAL bits of the input sample (per lane, both streams), i.e. the bits to the right of the binary point. Total width = integer + fractional bits, and must not exceed 64.
Fractional bits of one lane of both inputs. 0..64, total lane width 2..64 bits. Default 0.Default: 0
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Select whether the input sample (per lane, both streams) is signed (two’s complement) or unsigned.
SIGNED (two’s complement) or UNSIGNED lanes. Default SIGNED. Applies to every lane of both buses.Default: SIGNED
Options: UNSIGNED SIGNED
Number of INDEPENDENT time-multiplexed channels packed on the IN bus and on every result bus. Lane 0 occupies the LOW bits (lane 0 = the oldest sample of the clock), the same packing as every other TM block. All lanes share one EXP / IN_DV / frame; each lane gets its own accumulators, but the serial post-processing is ONE engine serving the lanes one after the other, so the tail latency (and the minimum usable EXP) grows with this factor.
Number of independent channel pairs packed on the buses, 2..16. Default 4. Multiplies BOTH input widths, the packed output width AND the serial tail length (the shared tail serves the lanes one after the other), so it also raises the minimum usable EXP.Default: 4
Options: 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Largest block-size exponent the accumulators are sized for: the block can be up to 2^MaxBlockExponent samples long. The EXP input is clamped to this value at run time. Raising it widens the internal accumulators, and ON THE BLOCKS WHOSE SERIAL ENGINES ARE SIZED FROM THOSE ACCUMULATORS (Coefficient of Variation, SNR, Skewness, Kurtosis, Correlation, Autocorrelation, Linear Regression) it also LENGTHENS THE SERIAL TAIL – even when the runtime EXP is small. Keep it at the largest block you actually use. The default of 20 covers blocks of up to 1048576 samples.
Largest block-size exponent the per-lane accumulators are sized for; the EXP input is clamped to it at run time. Raising it widens every lane’s accumulators. 1..31, default 20.Default: 20
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Number of INTEGER bits of the COVARIANCE output (per lane) (the sign, when present, uses one of them).
Integer bits of ONE LANE of the COVARIANCE output. 1..64, default 32.Default: 32
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Number of FRACTIONAL bits of the COVARIANCE output (per lane), i.e. the bits to the right of the binary point. Total width = integer + fractional bits, and must not exceed 64.
Fractional bits of one lane. 0..64, default 0.Default: 0
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Select whether the COVARIANCE output (per lane) is signed (two’s complement) or unsigned.
SIGNED or UNSIGNED lanes. Default SIGNED - a covariance is negative exactly when the two channels move in opposition, and that is the interesting case.Default: SIGNED
Options: UNSIGNED SIGNED
YES: the BUSY (high from the first sample of a block until its result is out – it COVERS THE SERIAL TAIL, and its last high clock IS the OUT_DV pulse) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared BUSY pin exists. Default NO.Default: NO
Options: NO YES
YES: the INTEGRATING (high only while the block is ACCUMULATING; it drops as soon as the N-th sample has been taken and the tail starts, so BUSY-and-not-INTEGRATING means ‘computing’) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared INTEGRATING pin exists. Default NO.Default: NO
Options: NO YES
YES: the SAMPLE_COUNT (32 bit, how many samples have been accumulated so far in the current block: 1 after the first, N after the N-th. It is NOT cleared at the block end – it holds N until the NEXT block’s first accepted sample takes it back to 1. On a CONTINUOUS stream that happens DURING the serial tail, so at OUT_DV it reads how far into the next block the input has already got, NOT N. To capture the length of the block being presented, latch SAMPLE_COUNT on the clock INTEGRATING falls – that one always reads N) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared 32 bit SAMPLE_COUNT pin exists. Default NO.Default: NO
Options: NO YES
ROUND: round to nearest when a result has to be requantised into a coarser output format. TRUNCATE: drop the bits (cheaper, adds a negative bias).
ROUND: round to nearest at each lane’s final requantisation. TRUNCATE: drop the bits. Default ROUND.Default: ROUND
Options: TRUNCATE ROUND
YES: clip to the largest representable value of each output format (symmetric for signed formats). NO: wrap around.
YES: clip each lane to its output format (symmetric for signed). NO: wrap. Default YES.Default: YES
Options: NO YES
Accuracy, per lane
Each lane is BIT EXACT, like the scalar twin: cov_num = NSab - SaSb is an exact integer (the serial |Sa|*|Sb| product is exact, the N scalings are shifts) and the division by N^2 is a shift. The harness demands tolerance 0 per lane. Like the scalar twin, a lane’s covariance CAN BE NEGATIVE - and negative is the interesting case - hence the SIGNED default output format; there is deliberately NO non-negativity clamp anywhere.
Timing: the TM latency contract
OUT_DV pulses ONCE per block, L clocks after the clock on which the
N-th sample was accepted, where
$$ L = 1 + \mathrm{TM},(\mathrm{IN_SW} + \mathrm{EXP} + 2) $$
(BCVT_TAIL in the core). ONE shared shift-add engine forms each lane’s
|Sa|*|Sb| in turn, so the tail DEPENDS ON THE RUNTIME EXPONENT, like the
scalar twin - the same shape as Block Variance TM. This is the family’s
lane-multiplexed rule $L_{tm}(e) = \mathrm{TM},(L_{scalar}(e)-1)+1$. At
the defaults (16 bit signed inputs, TM 4, EXP 10) that is 113 clocks, and
the minimum usable EXP is 7.
The family drop rule applies with the TM tail: the tail of one block must
finish before the NEXT block completes, $2^{{\mathrm{{EXP}}}} \ge L$, or the
completing block’s result is silently DROPPED (no OUT_DV, accumulators
unaffected, no error pin). The TM tail makes the minimum usable EXP larger
than the scalar twin’s - the compiler prints both the worst-case tail and
the minimum EXP in the compilation log, and the property window refuses a
configuration whose minimum exceeds Max Block Exponent.
Knowing where the block is: BUSY, INTEGRATING and SAMPLE_COUNT
Identical to the scalar family, and SHARED by all lanes: INTEGRATING is
high exactly while the block is accumulating (it dips one clock per block
boundary on a continuous stream), BUSY also covers the (TM-long) tail and
its last high clock IS the OUT_DV pulse, SAMPLE_COUNT reads 1 after the
first accepted sample pair and N after the N-th.
SAMPLE_COUNTis NOT cleared at the block end - it holds N until the NEXT block’s first accepted sample takes it back to 1. On a CONTINUOUS stream that happens DURING the serial tail (which on a TM block is TM Factor times longer), so atOUT_DVit reads how far into the next block the input has got, NOT N. The clock that always reads N is the oneINTEGRATINGfalls on - latch it there.
Verification
The core is regression tested by a host-side csim harness
(tb/block-ops-tm/run_tb_tm.ps1) with per-lane goldens computed by
gen_golden_tm.py in exact rational arithmetic ON EACH LANE PAIR’S STREAMS
ALONE (lanes deliberately carry different signals - the generator refuses
identical lanes), plus the strongest available lane-independence check:
after every run, the SCALAR twin is replayed on each lane pair’s streams by
themselves and lane k of every TM result must match it BIT FOR BIT. The
status waveform is checked clock by clock, every packed output is checked
to move only on OUT_DV, and the TM-specific mutant classes (shared
accumulator, lane swaps on either bus, wrong-lane tail reads, early commit,
drop rule) are killed. What no host harness can prove - that Vitis accepts
and schedules the core at II=1 - is stated in AGENT/block_ops.log, not
silently implied.