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Introduction

TDCSync implements a synchronous Time-to-Digital Converter suitable for timestamping digital pulses with high resolution.

The core functionality is based on a 48-bit free-running counter clocked by a fast clock source. When an input signal transition is detected, the current counter value is latched and transferred to the output domain through a CDC (Clock Domain Crossing) handshake mechanism.

The timestamp resolution is determined by the fast clock frequency:

$$ \Delta t = \frac{1}{f_{\text{FAST_CLK}}} $$

For example, with a 500 MHz fast clock, the resolution is 2 ns.

Pin Description

IN Input 1 bit BIT
Input signal to be timestamped. The edge polarity is configurable via the Signal Edge property.
RUN Input 1 bit BIT
Counter enable. When high, the timestamp counter increments. When low, the counter is frozen. Default value: 1 (always running).
T0 Input 1 bit BIT
Counter reset signal (synchronous to FAST_CLK). Resets the 48-bit counter to zero on the configured edge. The edge polarity is configurable via the T0 Edge property.
CLK Input 1 bit BIT
Output data clock. The timestamp output and DV signal are synchronous to this clock. Use the default board acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Global synchronous reset. Resets the counter and all internal state.
Default: Default Board Reset
CLKFAST Input 1 bit BIT
Fast clock input (optional). Only visible when Clock Source property is set to “External”. Drives the timestamp counter.
TIMESTAMP Output 48 bit BIT VECTOR
48-bit timestamp output. Contains the counter value latched at the input signal edge. Valid only when DV = 1.
DV Output 1 bit BIT
Data Valid strobe. High for one CLK cycle when a new timestamp is available on the TIMESTAMP output.

Properties

Property window

Clock Source ClkSource

Set clock source for the TDC

Selects the clock source for the TDC counter. Available options: Board, Acquisition, 100MHz, 200MHz, 250MHz, 500MHz, External.

Default: Board

Options: Board Acquisition 100MHz 200MHz 250MHz 500MHz External

Signal Edge EdgeSignal

Set the EDGE of the input signal used to trigger the TDC

Selects which edge of the input signal triggers timestamp capture. Options: Rising, Falling.

Default: Rising

Options: Rising Falling

T0 Edge EdgeT0

Set the EDGE of the T0 used to reset the TDC

Selects which edge of the T0 signal resets the counter. Options: Rising, Falling.

Default: Rising

Options: Rising Falling

Usage

Functional overview

TDCSync operates with two clock domains:

  • FAST_CLK: High-frequency clock driving the timestamp counter
  • CLK: Output clock domain for data readout

The architecture consists of:

Block Function
48-bit Counter Free-running counter incremented at FAST_CLK rate
Edge Detector Detects signal transitions based on configured polarity
Timestamp Latch Captures counter value on input edge
CDC Handshake Transfers timestamp safely across clock domains

TDC Block Diagram

Operation

  1. The 48-bit counter runs continuously at the FAST_CLK frequency
  2. The counter can be reset to zero via the T0 input
  3. When the RUN signal is high, the counter increments
  4. On each detected edge of IN, the counter value is latched
  5. The latched value is transferred to the CLK domain via CDC logic
  6. DV pulses high when a valid timestamp is available on TIMESTAMP

Clock Domain Crossing

The block uses a Xilinx XPM CDC handshake primitive (xpm_cdc_handshake) to safely transfer the 48-bit timestamp from the FAST_CLK domain to the CLK domain. This ensures:

  • No metastability issues
  • No data corruption
  • Proper synchronization

Maximum Event Rate

Due to the CDC handshake overhead, the maximum event rate is limited to:

$$ f_{\text{max}} = \frac{f_{\text{CLK}}}{4} $$

For a 125 MHz CLK, this corresponds to ~31 MHz maximum event rate.

Clock Source Options

The fast clock source can be configured via the Clock Source property:

Option Description
Board Use the board’s default clock
Acquisition Use the acquisition clock
100MHz Use internal 100 MHz clock
200MHz Use internal 200 MHz clock
250MHz Use internal 250 MHz clock
500MHz Use internal 500 MHz clock
External Use external clock via CLKFAST pin

Timing Resolution Examples

Fast Clock Resolution Counter Overflow Time
100 MHz 10 ns ~32 days
200 MHz 5 ns ~16 days
250 MHz 4 ns ~13 days
500 MHz 2 ns ~6.5 days