TM
Block Preview

Introduction

This block performs a bitwise AND operation on time-multiplexed (TM) data streams. Supports two operation modes:

  • TM mode: Both IN1 and IN2 are TM, element-wise AND per phase
  • STD mode: IN1 is TM, IN2 is scalar mask applied to all phases

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT}(n) = \mathrm{IN1}(n) \land \mathrm{IN2}(n), $$

where $\land$ represents the logical AND operation.

Pin Description

IN1 Input Variable bit TM
First input data, always TM. Width: Input Size × TM Factor
Default: Must be connected
IN2 Input Variable bit TM

Second input data, TM or scalar (configurable).

  • TM mode: Width = Input Size × TM Factor
  • STD mode: Width = Input Size (applied to all phases)
Default: Must be connected
OUT Output 16 bit TM
AND result output, always TM. Width: Input Size × TM Factor Output is combinational (zero latency).

Properties

Property window

Input size (bits) InputSize

Set the size of each input in bits

Number of bits per input sample. Range: 1 – 16384.

Default: 16

Range: 1 – 16384

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Time-multiplexing factor (number of parallel phases). Range: 2 – 32.

Default: 4

Range: 2 – 32

IN2 Mode IN2_Mode

Specify if IN2 input is Time Multiplexed (TM) or Standard (STD). STD mode allows using a constant mask applied to all TM phases.

Input mode for IN2: TM (time-multiplexed, element-wise AND) or STD (scalar mask applied to all TM phases).

Default: TM

Options: TM STD

Functional description

The component implements a bitwise AND gate in VHDL, replicated N times (where N = TM Factor) to support time-multiplexed data streams.

For each TM phase and each bit position:

$$ y[i] = x_1[i] \land x_2[i], $$

where:

  • $x_1[i]$ → bit $i$ of first input
  • $x_2[i]$ → bit $i$ of second input (TM or scalar)
  • $y[i]$ → bit $i$ of the output
  • $\land$ → logical AND operation

Truth table for AND operation:

IN1 IN2 OUT
0 0 0
0 1 0
1 0 0
1 1 1

Input modes

  • IN2 Mode = TM: IN2 is time-multiplexed, element-wise AND for each phase
  • IN2 Mode = STD: IN2 is scalar mask, same value applied to all TM phases

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Logic AND TM 0

All TM phases are processed in parallel.

Typical use cases

  • Bitwise masking of TM data streams
  • Signal gating and enable logic
  • Building complex boolean functions
  • Multi-channel data filtering