Xilinx
HLS
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Introduction

The Complex + Constant block adds a compile-time complex constant to each incoming sample:

      OUT_I[n] = IN_I[n] + OffsetI
    OUT_Q[n] = IN_Q[n] + OffsetQ

The two offsets are entered as signed integer text properties (OffsetI, OffsetQ) and baked into the netlist as internal constant signals. They are not exposed as fabric pins: the plugin sign-extends each value to OffsetSize bits, packs it as a VHDL constant and wires it to an ap_stable port on the HLS core.

Pin Description

IN_I Input InputSize bit BIT VECTOR
In-phase (I) input sample. Signed, Input Bit Width bits.
Default: Must be connected
IN_Q Input InputSize bit BIT VECTOR
Quadrature (Q) input sample. Signed, Input Bit Width bits.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
HLS synchronous reset (ap_rst). Default: Global reset. The block is stateless, so reset does not affect the output value.
Default: Default Board Reset
OUT_I Output max(InputSize, OffsetSize) + 1 bit BIT VECTOR
In-phase (I) output = IN_I + OffsetI. Signed, max(InputSize, OffsetSize) + 1 bits.
OUT_Q Output max(InputSize, OffsetSize) + 1 bit BIT VECTOR
Quadrature (Q) output = IN_Q + OffsetQ. Signed, max(InputSize, OffsetSize) + 1 bits.

Properties

Property window

Input Bit Width InputSize

Bit width of each I/Q input (signed).

Bit width of each signed I / Q input sample. Range 4 to 32, default 16.

Default: 16

Options: 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Offset Bit Width OffsetSize

Bit width of each offset constant (signed).

Bit width of each signed offset constant. Range 4 to 32, default 16. Must be wide enough to hold the offset values you enter.

Default: 16

Options: 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Offset I (signed integer) OffsetI

Constant added to the I channel.

Constant added to the I channel, entered as a signed decimal integer. Default 0. Encoded as a two’s-complement OffsetSize-bit constant.

Default: 0

Offset Q (signed integer) OffsetQ

Constant added to the Q channel.

Constant added to the Q channel, entered as a signed decimal integer. Default 0. Encoded as a two’s-complement OffsetSize-bit constant.

Default: 0

Usage

Mathematical model 

      OUT = IN + OFFSET       (per channel, signed integer add)

The add is done at full precision, so the result can grow by at most one bit versus the wider of the two operands.

Bit widths

Data and offsets are signed two’s complement.

  • IN_I, IN_Q : signed InputSize bits.
  • OffsetI, OffsetQ : signed OffsetSize-bit constants (internal).
  • OUT_I, OUT_Q : signed max(InputSize, OffsetSize) + 1 bits.

The +1 guard bit guarantees the sum never overflows regardless of the relative sizes of the input and the constant.

Constant encoding

Each offset property is parsed as a signed decimal integer, masked to OffsetSize bits (two’s complement) and emitted as a hex constant in the VHDL. Choose OffsetSize large enough to represent the offset you type: a value outside the signed OffsetSize-bit range wraps.

Latency and throughput

  • #pragma HLS PIPELINE II=1 : one sample pair per clock.
  • 1-clock latency.
  • Data ports use ap_none; the offset ports use ap_stable.
  • #pragma HLS INTERFACE ap_ctrl_none port=return : no block-level control.

This block is stateless feed-forward arithmetic; RESET has no effect on the output value (the port exists only for standard HLS reset wiring).

Typical applications

  • DC-offset injection for calibration or test.
  • DC correction by adding the negative of a measured bias (pair with the Complex DC Blocker for automatic tracking instead).
  • Re-centering a signed stream around a non-zero operating point.

Resources & Timing

  • Latency: 1 clock cycle

  • Throughput: 1 sample per clock (II=1)

Two adders (one per channel), no multipliers, no BRAM. Stateless. Because the offsets are compile-time constants Vivado optimises a zero offset away entirely.