Xilinx
Block Preview

Introduction

Every CE clock the block outputs $-\ln(u) \cdot 2^{F}$ with $u$ uniform in $(0,1]$: an exponential distribution with mean (and sigma) $2^{F}$ LSB. Useful for amplitude spectra with exponential tails, service/decay time emulation, or as the inter-arrival generator of event models.

$-\ln u$ is computed as $-\log_2(u) \cdot \ln 2$: the integer part of $-\log_2$ comes from the leading-zero count (exact), the fractional part from a 1024-entry mantissa LUT (Q0.16), then one constant multiply by $\ln 2$ and a rounded shift to the output Q format.

Exponential distribution

The log-scale histogram (measured on the bit-exact model the hardware is verified against) is a straight line over more than three decades.

Pin Description

CE Input 1 bit BIT
Clock enable: one new sample per clock where high. Default: ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Restarts the sequence from the seed.
Default: Default Board Reset
OUT Output 16 bit BIT VECTOR
Exponential sample, UNSIGNED, OutputBits wide, saturated.
DV_OUT Output 1 bit BIT
High on every clock carrying a new sample.

Properties

Property window

Output bits OutputBits

Width of the OUT word (2..32), UNSIGNED, saturated.

Output width (2..32), unsigned, saturated.

Default: 16

Range: 2 – 32

Fract bits FractBits

Output Q format: OUT = -ln(u) * 2^FractBits. The distribution MEAN is 2^FractBits LSB.

Output Q format (0..16): OUT = -ln(u)*2^FractBits, mean = 2^FractBits LSB.

Default: 10

Range: 0 – 16

SEED (32 digit hex) SEED

Seed of the embedded white generator (128 bit hex), expanded internally with SplitMix64. Auto-randomized when the component is created, so multiple instances produce independent noise; editable for reproducible runs. RESET restarts the sequence. Exponential distribution: OUT = -ln(u)*2^FractBits, unsigned, mean = 2^FractBits LSB.

128-bit seed of the embedded white generator (auto-randomized at placement, editable).

Default: 6CF5ACF82878454F8F5E3866DB7AF6D0

Usage

Latency 4 CE-clocks (DV marks valid outputs), throughput one sample per CE clock. RESET restarts the sequence; CE defaults to ‘1’.