Xilinx
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Introduction

The block performs floating-point addition of two IEEE-754 encoded values. On every rising edge of CLK, if both A_CE = 1 and B_CE = 1, the adder computes

$$ \mathrm{F}(n) = \mathrm{A}(n) + \mathrm{B}(n), $$

where inputs A, B and output F follow IEEE-754 single or double precision format.

The addition is implemented with the Xilinx floating_point IP core configured for Add operation with blocking flow control, fixed 12-cycle latency, and configurable DSP primitive usage for optimized performance.

Pin Description

A Input Variable bit BIT VECTOR
First floating-point addend (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Accepted when A_CE = 1 and A_READY = 1.
Default: Must be connected
A_CE Input 1 bit BIT
Input A Clock Enable (tvalid), active high. When A_CE = 1, input A is accepted into the pipeline. Can be tied to ‘1’ for continuous operation.
B Input Variable bit BIT VECTOR
Second floating-point addend (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Accepted when B_CE = 1 and B_READY = 1.
Default: Must be connected
B_CE Input 1 bit BIT
Input B Clock Enable (tvalid), active high. When B_CE = 1, input B is accepted into the pipeline. Can be tied to ‘1’ for continuous operation.
READY_IN Input 1 bit BIT
Downstream ready signal (tready input), active high. Indicates if downstream logic can accept new result data. Can be tied to ‘1’ if backpressure is not needed.
CLK Input 1 bit BIT
Global clock. Every rising edge triggers pipeline advancement. Connected to system acquisition clock.
Default: Default Board Clock
F Output 32 bit BIT VECTOR
Floating-point sum output (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Valid when DV = 1. Result = A + B.
DV Output 1 bit BIT
Data Valid output (tvalid), active high. Indicates when output F contains a valid sum. Asserts 12 clock cycles after corresponding inputs accepted.
A_READY Output 1 bit BIT
Input A ready signal (tready output), active high. Indicates this block can accept new data on input A. Used for flow control on A channel.
B_READY Output 1 bit BIT
Input B ready signal (tready output), active high. Indicates this block can accept new data on input B. Used for flow control on B channel.

Properties

Property window

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Floating-point precision for all inputs and output:

  • Single → 32-bit (8-bit exponent, 24-bit mantissa including implicit bit)
  • Double → 64-bit (11-bit exponent, 53-bit mantissa including implicit bit)

All operands must use the same precision.

Default: Single

Options: Single Double

DSP Usage DSPUsage

DSP Usage. Single precision: No [0], Full[2]. Double precision: No[0], Full[3]

DSP primitive allocation strategy:

  • No_Usage → LUT-only implementation (0 DSPs, lower speed)
  • Full_Usage → DSP-optimized (2/3 DSPs for Single/Double, higher speed)

Full usage improves maximum clock frequency at the cost of DSP resources.

Default: Full_Usage

Options: No_Usage Full_Usage

Functional description

The component performs IEEE-754 compliant floating-point addition:

$$ F = A + B $$

The operation handles:

  • Exponent alignment (denormalizing the smaller operand)
  • Mantissa addition with guard/round/sticky bits
  • Result normalization
  • Rounding (round-to-nearest, ties-to-even)

Special cases

IEEE-754 special value handling:

  • +0 + +0 = +0
  • +Inf + x = +Inf (for finite x)
  • +Inf + -Inf = NaN (invalid operation)
  • NaN + x = NaN (NaN propagation)

DSP Usage

The DSP Usage property controls resource allocation:

Single precision:

  • No_Usage → Pure LUT implementation (0 DSPs)
  • Full_Usage → Optimized with DSP48 primitives (2 DSPs)

Double precision:

  • No_Usage → Pure LUT implementation (0 DSPs)
  • Full_Usage → Optimized with DSP48 primitives (3 DSPs)

Full DSP usage improves timing at the cost of DSP resources.

Timing

The IP has a fixed 12-cycle pipeline latency:

Clock cycle Event
0 Inputs A, B presented with A_CE = 1, B_CE = 1
12 Output F valid with DV = 1

The separate A_READY/B_READY handshake signals enable independent backpressure control for each input.

Typical use cases

  • Vector arithmetic in signal processing
  • Accumulation in digital filters
  • Complex number arithmetic (real + imaginary components)
  • Scientific computing pipelines