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Introduction

The Gated Integrator accumulates input samples over a programmable time window (gate length), multiplies by a gain factor, and produces a single output value:

$$ \mathrm{OUT} = \mathrm{GAIN} \times \sum_{i=0}^{G-1} \mathrm{IN}[i] $$

where G is the gate length. This is commonly used in nuclear instrumentation for charge integration, energy measurement, and pulse-height analysis.

The block includes handshake signals (DV_OUT, READY) for synchronization with downstream processing stages.

Pin Description

DATA_IN Input 32 bit BIT VECTOR
Input data stream to be integrated. Width: 32 bits (signed fixed-point). Typically ADC output or preprocessed detector signal.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable / Trigger input, active high. Controls integration timing. Default: tied to ‘1’ (free-running).
Default: 1
GATE Input 16 bit BIT VECTOR
Integration window length in clock cycles. Width: 16 bits (unsigned integer). Range: 1 to 65535. Determines how many samples are accumulated. Default: 16 (x"0010").
GAIN Input 32 bit BIT VECTOR
Gain scaling factor applied to integrated sum. Width: 32 bits (signed fixed-point, Q16.16 format typical). Common values: x"00010000" (gain = 1.0), x"00008000" (gain = 0.5). Default: x"00010000" (unity gain).
CLEAR Input 1 bit BIT
Asynchronous clear signal, active high. Immediately resets accumulator and state machine. Default: tied to ‘0’ (inactive).
CLK Input 1 bit BIT
System clock. Drives accumulation and output state machine.
Default: Default Board Clock
OUT Output 32 bit BIT VECTOR
Integrated and scaled output. Width: 32 bits (signed fixed-point). Valid when DV_OUT is high.
DV_OUT Output 1 bit BIT
Data Valid output signal, active high. Pulses high for one clock cycle when integration result is ready.
READY Output 1 bit BIT
Ready signal, active high. Indicates integrator is idle and ready to start new integration.

Functional description

The gated integrator performs windowed accumulation followed by gain scaling:

  1. Accumulation phase: Sums GATE consecutive input samples
  2. Scaling phase: Multiplies accumulated sum by GAIN
  3. Output phase: Asserts DV_OUT and presents result on OUT

Operation modes

  • Continuous: Automatically starts new integration after each cycle
  • Triggered: External trigger controls integration start (via CE)
  • Clear: CLEAR signal resets accumulator immediately

Fixed-point arithmetic

All inputs and outputs use 32-bit signed fixed-point format:

  • DATA_IN: Input samples (32 bits, signed)
  • GAIN: Scaling factor (32 bits, signed, typically Q16.16 format)
  • OUT: Integrated and scaled result (32 bits, signed)

Handshake protocol

  • CE: Clock enable / trigger input
  • DV_OUT: Data valid output (high for one cycle when result ready)
  • READY: Ready for new integration (high when idle)

Latency

Fixed latency of 4 clock cycles from gate completion to output valid.

Typical use cases

  • Charge integration in PMT and SiPM readout
  • Energy measurement in gamma spectroscopy
  • Pulse-height analysis in nuclear physics
  • Shaping amplifier replacement in digital systems