FFT Average [TM]

Introduction link

Averaging $M$ spectra of a stationary signal reduces the noise-floor variance by $M$ while leaving coherent lines untouched:

$$ \bar{X}[k] = \frac{1}{2^{NAVG}}\sum_{m=0}^{2^{NAVG}-1} X_m[k] $$

The block consumes the gapless TM spectrum format of FFT TM Realtime and FFT Windowed TM: every CE-gated clock carries $R$ bins (TM Factor lanes), with lane $q$ carrying bin $k + q,N/R$ at DV cycle $k$ and START (chain FRAME_START) marking the first cycle of each frame. Each lane is accumulated independently into a BRAM accumulator; when $2^{NAVG}$ complete spectra have been summed the averaged spectrum streams out.

Two output formats are available (compile-time property, both from the same accumulator):

• TM (R bins per clock) — the average leaves in exactly the input packing and lane mapping, as an $N/R$-clock burst: drop-in for anything that already consumes the TM FFT stream (e.g. IFFT TM Realtime).
• Serialized (one bin per clock) — the average leaves as a non-TM sequential burst in natural bin order $0 \ldots N-1$ ($N$ clocks), i.e. the same format the scalar FFT block emits: chain it to the scalar IFFT, to a DMA, or to any scalar-burst consumer. The serializer sweeps the accumulator once per lane (lane $q$ outer, row $k$ inner), which is exactly natural order thanks to the TM lane mapping.

NAVG is a runtime input (log2 of the number of spectra, e.g. 10 → 1024), clamped to the compile-time Max averages budget and latched at the start of every round. The accumulator is ping-pong double buffered, so accumulation of the next round proceeds while the previous average streams out and its memory is cleared row by row.

Pin Description link

Properties link

Chaining from the TM FFT blocks link

• OUT_RE → IN_RE, OUT_IM → IN_IM (TM pins, same TM Factor)
• FRAME_START → START
• DV → CE

Leaving CE unconnected ties it to ‘1’; leaving NAVG unconnected gives $2^0 = 1$ (passthrough).

Output scaling link

Same options as the scalar FFT Average:

• Same as input (rounded) — each output bin is InputBits wide, average rounded half-up. No overflow is possible.
• Fixed point (+16 fractional bits) — each output bin is InputBits + 16 wide and exact; the 16 extra LSBs are fractional bits with the input integer scaling (Q x.16, ready for the Fixed P. family).

Round lifecycle link

1. Every CE clock accumulates one TM row ($R$ bins); START resynchronizes the row counter.
2. AVG_CNT reports in realtime how many complete spectra of the current round have been accumulated.
3. When the round completes the buffers swap and the average streams out (START_OUT + DV_OUT, BUSY high for the whole burst): $N/R$ clocks in TM mode, $N$ clocks serialized. Rows are cleared right after their last read.
4. CLR (or RESET) discards the round in progress and restarts from zero.

Throughput limit of the serialized output link

The serialized burst is $N$ clocks while a round lasts at least $(N/R)\cdot 2^{NAVG}$ input clocks: with gapless TM input, choose $NAVG \geq \log_2 R$ (e.g. $R = 4$ → at least 4 averages) or rounds that complete while the previous burst is still streaming are dropped (accumulation itself never stops, and the TM output mode only has the scalar $NAVG = 0$ corner). In practice any real averaging setting is safe.

Resources link

Two BRAM buffers of $N/R$ rows, each row $2R,(\text{InputBits} + \log_2\text{MaxAverages})$ bits — the total bit count is the same as the scalar block for equal $N$. No DSP, no HLS: pure VHDL.

Verified with a self-checking GHDL regression (4 TM configurations — TM and serialized outputs, TM factors 2/4/8, both scalings — 556 checks: lane mapping, natural-order serialization, rounding on negative accumulations, CE gaps, buffer reuse, mid-round CLR, runtime NAVG change, DV/START_OUT/BUSY framing, AVG_CNT progress; mutation-tested).