Xilinx
HLS
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Introduction

The CORDIC Polar -> Rect block is the inverse of Component_ComplexAtan2. Given a magnitude and a phase it reconstructs the complex sample:

      OUT_I = MAG * cos(PHASE) * K_cordic
    OUT_Q = MAG * sin(PHASE) * K_cordic

It runs the CORDIC algorithm in rotation mode: starting from the vector (x, y) = (MAG, 0) it rotates by the requested angle PHASE in successively smaller steps atan(2^-k), driving the angle accumulator z towards zero. Each step is a shift and an add/sub - no multipliers, no sin/cos ROM.

The phase uses the same full-scale convention as the atan2 block, so the two are directly composable (rect -> polar -> rect).

Pin Description

MAG Input MagSize bit BIT VECTOR
Magnitude input. Unsigned, Magnitude Bit Width bits. Pre-scale by ~0.607 if you need to cancel the CORDIC 1.647x gain.
Default: Must be connected
PHASE Input 16 bit BIT VECTOR
Phase input, signed 16 bits with +/-Pi = +/-32768. Compatible with the PHASE output of Component_ComplexAtan2 and with the NCO phase.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
HLS synchronous reset (ap_rst). Default: Global reset.
Default: Default Board Reset
OUT_I Output OutSize bit BIT VECTOR
In-phase output ~= 1.647 * MAG * cos(PHASE). Signed, OutSize bits.
OUT_Q Output OutSize bit BIT VECTOR
Quadrature output ~= 1.647 * MAG * sin(PHASE). Signed, OutSize bits.

Properties

Property window

Magnitude Bit Width MagSize

Bit width of the magnitude input (unsigned).

Bit width of the unsigned magnitude input. Range 8 to 32, default 18.

Default: 18

Options: 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Output Bit Width OutSize

Bit width of each I/Q output (signed). Includes CORDIC 1.647x gain.

Bit width of each signed I / Q output. Range 8 to 32, default 18. Choose it to accommodate the ~1.647x CORDIC gain, or pre-scale the magnitude to cancel it.

Default: 18

Options: 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

CORDIC Iterations NIter

Number of CORDIC iterations. 16 gives ~15-bit precision. Latency = NIter clocks.

Number of CORDIC iterations. Selectable 8, 12, 16, 20; default 16 (~15-bit precision). Latency equals NIter clocks. Values above 16 add latency without extra angle resolution (16-bit angle LUT exhausted past iteration 15).

Default: 16

Options: 8 12 16 20

Usage

Phase scaling

PHASE is a signed 16-bit value with +/-Pi mapped to +/-2^15:

      +Pi   = +32768 (wraps)     +Pi/2 = +16384
    0     = 0                  -Pi/2 = -16384

This matches Component_ComplexAtan2 and the NCO, so a phase accumulator or an atan2 output can drive this block unchanged.

Convergence-range folding

CORDIC rotation only converges for |angle| <= ~Pi/2. For |PHASE| > Pi/2 the block first does a 180-degree pre-rotation (negate x) and shifts z by Pi, so the iterative part always sees |z| < Pi/2:

      z > +Pi/2 (=16384) : z -= Pi (32768), x = -x
    z < -Pi/2          : z += Pi,          x = -x

Iterations and the angle LUT

Each iteration k = 0 .. N_ITER-1 rotates by +/-atan(2^-k), taken from the same table as the atan2 block:

      ATAN_LUT[k] = round(atan(2^-k) * 32768 / Pi)
    k :  0     1     2     3    4    5    6   7   8  ...
    LUT: 8192  4836  2555  1297 651  326  163 81  41 ...
  
      N_ITER   angle precision    latency
    8        ~8 bits            8 clocks
    12       ~12 bits           12 clocks
    16       ~15 bits (default) 16 clocks
    20       ~15 bits (LUT exhausted past k=15)

The CORDIC gain (NOT compensated)

The output carries the CORDIC processing gain K_cordic ~= 1.647:

      OUT_I = 1.647 * MAG * cos(PHASE)
    OUT_Q = 1.647 * MAG * sin(PHASE)

This block does not remove the gain. If you need unity gain, pre-scale the magnitude input by 0.607 (~= 1 / 1.647) before this block. For most uses (modulation, rotating an existing complex vector) the 1.647x is simply absorbed into a downstream scale or AGC.

Bit widths

  • MAG : unsigned MagSize bits.
  • PHASE : signed 16 bits (fixed, Pi = 32768).
  • OUT_I, OUT_Q : signed OutSize bits. Internally the datapath uses OutSize + 2 guard bits to hold the CORDIC gain before the final truncation to OutSize.

Defaults: MagSize = 18, OutSize = 18. Size OutSize so that 1.647 * MAG_full_scale fits, or pre-scale as above.

Latency and throughput

  • #pragma HLS PIPELINE II=1 : one sample per clock.
  • The N_ITER iterations are fully unrolled and pipelined: latency is N_ITER clocks (default 16), throughput one sample per clock. (The schematic symbol reports a nominal latency of 16.)
  • All ports use the ap_none interface (no ready/valid handshake).

Reset

RESET is the HLS synchronous reset (ap_rst) and clears the pipeline registers.

Typical applications

  • IQ modulator : feed a baseband envelope on MAG and a phase ramp on PHASE to synthesise a modulated carrier.
  • Phase rotator : combine with Component_ComplexAtan2 to rotate a complex stream by an arbitrary angle (rect -> polar, add angle, polar -> rect).
  • Arbitrary-amplitude DDS : drive PHASE from a phase accumulator and MAG from an amplitude profile.
  • Sin/cos generation : hold MAG constant and sweep PHASE.

Resources & Timing

  • Latency: NIter clock cycles (default 16)

  • Throughput: 1 sample per clock (II=1)

Multiplier-free: NIter fully-unrolled shift-and-add rotation stages plus a small constant angle LUT (no sin/cos ROM). Output carries an uncompensated ~1.647x CORDIC gain - pre-scale MAG by ~0.607 for unity. Phase resolution bounded by the 16-bit phase word (Pi = 32768).