Block Preview

Introduction

This block generates a constant floating-point value conforming to the IEEE-754 standard. The component converts a decimal floating-point value (e.g., 3.14159, 6.022e23) into binary IEEE-754 representation.

Two precision modes are supported:

  • IEEE-754 SINGLE: 32-bit format (1 sign + 8 exponent + 23 mantissa bits)
  • IEEE-754 DOUBLE: 64-bit format (1 sign + 11 exponent + 52 mantissa bits)

The output is purely combinational with zero clock latency, suitable for direct use in floating-point arithmetic pipelines or as initialization values.

Pin Description

CONST Output Variable (32 or 64 bits) bit BIT VECTOR

Constant floating-point output in IEEE-754 binary format, always combinational (zero latency). Width: 32 bits (SINGLE) or 64 bits (DOUBLE), determined by FloatingMode property.

The output is a bit-accurate representation of the specified floating-point value, ready for direct use in IEEE-754 compliant arithmetic units.

Properties

Property window

Name Name

Set the value of the constant. Can be left blank

Optional custom label for the component. If specified, replaces the default title “Const Floating Point” on the schematic symbol. Leave blank to use default.
Value Value

Set the value of the constant.

Floating-point constant value in decimal notation. Supports standard formats: 3.14159, -2.5e-10, 6.022e23. Use comma or period as decimal separator. Automatically converted to IEEE-754 binary.

Default: 0

Float Standard FloatingMode

Set floating point standard between SINGLE and DOUBLE

IEEE-754 precision standard. Choose “IEEE-754 SINGLE” for 32-bit format (~7 digit precision, range ±10^38) or “IEEE-754 DOUBLE” for 64-bit format (~15 digit precision, range ±10^308).

Default: IEEE-754 SINGLE

Options: IEEE-754 SINGLE IEEE-754 DOUBLE

Functional description

The component implements an IEEE-754 floating-point constant source. Given a decimal value $V$ and precision mode, the output is:

$$ \mathrm{CONST} = \text{IEEE-754}(V, \text{mode}) $$

where the binary representation follows the IEEE-754 standard encoding.

IEEE-754 format structure

Single precision (32 bits) 

  | Sign (1) | Exponent (8) | Mantissa (23) |
|    S     |   EEEEEEEE   | MMMMMMMMMMMMMMMMMMMMMMM |

Value representation: $$ V = (-1)^S \times 1.M \times 2^{(E-127)} $$

  • Range: $\pm 1.18 \times 10^{-38}$ to $\pm 3.40 \times 10^{38}$
  • Precision: ~7 decimal digits
  • Exponent bias: 127

Double precision (64 bits) 

  | Sign (1) | Exponent (11) |      Mantissa (52)       |
|    S     | EEEEEEEEEEE   | MMMMMMMMMMMMMMMMMMMM...  |

Value representation: $$ V = (-1)^S \times 1.M \times 2^{(E-1023)} $$

  • Range: $\pm 2.23 \times 10^{-308}$ to $\pm 1.80 \times 10^{308}$
  • Precision: ~15 decimal digits
  • Exponent bias: 1023

Special values

IEEE-754 defines special bit patterns for non-finite values:

Value Sign Exponent (SP) Mantissa
+0.0 0 0x00 0x000000
-0.0 1 0x00 0x000000
+Infinity 0 0xFF 0x000000
-Infinity 1 0xFF 0x000000
NaN (quiet) X 0xFF non-zero

The component automatically handles these special cases during conversion.

Conversion example: π in single precision

Given:

  • Value = 3.14159265
  • Mode = IEEE-754 SINGLE

Conversion steps:

  1. Sign bit: 0 (positive)
  2. Normalize: $3.14159265 = 1.57079633 \times 2^1$
  3. Exponent: $1 + 127 = 128 = 0x80$
  4. Mantissa: $.57079633 \approx 0.10010010000111111011011$ (23 bits)
  5. Binary: 0 10000000 10010010000111111011011
  6. Hex: 0x40490FDB

Precision considerations

Single precision is suitable for:

  • General-purpose floating-point arithmetic
  • Graphics and signal processing (where ~7 digits is sufficient)
  • Resource-constrained FPGA designs (saves 32 bits per value vs. double)

Double precision is necessary for:

  • Scientific computing requiring high accuracy
  • Numerical algorithms sensitive to rounding errors
  • Financial calculations or precise physical constants

Rounding behavior

The conversion from decimal to binary uses the round-to-nearest-even (banker’s rounding) mode, which is the default IEEE-754 rounding mode. This minimizes cumulative rounding bias.

Implementation details

The VHDL implementation generates the IEEE-754 binary string at compile time:

vhdl 
  signal CONST : STD_LOGIC_VECTOR(BitSize-1 downto 0);
CONST <= "<IEEE-754 binary representation>";

The .NET BitConverter class performs the decimal-to-binary conversion, ensuring full IEEE-754 compliance including handling of denormals, infinities, and NaN values.

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Constant Floating-Point 0

The output is available immediately after FPGA configuration.

Typical use cases

  • Mathematical constants: Define π, e, √2, or physical constants (c, G, h, etc.)
  • Floating-point pipelines: Provide constant multipliers, divisors, or offsets
  • DSP algorithms: Supply filter coefficients in floating-point format
  • Scientific computing: Store predefined physical or mathematical values
  • Calibration factors: Floating-point scaling or correction constants
  • Machine learning: Neural network weights or bias values (in FP32/FP64 networks)

Example configurations

Example 1: Pi constant (single precision) 

  Name: "PI"
Value: 3.14159265
FloatingMode: IEEE-754 SINGLE
Output: 32 bits = 0x40490FDB

Example 2: Avogadro’s number (double precision) 

  Name: "Na"
Value: 6.02214076e23
FloatingMode: IEEE-754 DOUBLE
Output: 64 bits = 0x44B52D02C7E14AF6

Example 3: Small fractional constant 

  Value: 0.001
FloatingMode: IEEE-754 SINGLE
Output: 32 bits = 0x3A83126F

Example 4: Negative constant 

  Value: -273.15
FloatingMode: IEEE-754 DOUBLE
Output: 64 bits (sign bit = 1)