Xilinx
HLS
Block Preview

Introduction

The Complex Add block sums two complex baseband samples per clock:

      OUT_I[n] = A_I[n] + B_I[n]
    OUT_Q[n] = A_Q[n] + B_Q[n]

Equivalently, with A = A_I + j*A_Q and B = B_I + j*B_Q,

      OUT = A + B

Both inputs are treated as signed two’s complement. The output is one bit wider than the inputs (InputSize + 1) so the sum never overflows.

Pin Description

A_I Input InputSize bit BIT VECTOR
In-phase (I) part of operand A. Signed, Input Bit Width bits.
Default: Must be connected
A_Q Input InputSize bit BIT VECTOR
Quadrature (Q) part of operand A. Signed, Input Bit Width bits.
Default: Must be connected
B_I Input InputSize bit BIT VECTOR
In-phase (I) part of operand B. Signed, Input Bit Width bits.
Default: Must be connected
B_Q Input InputSize bit BIT VECTOR
Quadrature (Q) part of operand B. Signed, Input Bit Width bits.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
HLS synchronous reset (ap_rst). Default: Global reset.
Default: Default Board Reset
OUT_I Output InputSize + 1 bit BIT VECTOR
In-phase (I) output = A_I + B_I. Signed, InputSize + 1 bits.
OUT_Q Output InputSize + 1 bit BIT VECTOR
Quadrature (Q) output = A_Q + B_Q. Signed, InputSize + 1 bits.

Properties

Property window

Input Bit Width InputSize

Bit width of each I/Q sample (signed). Output is InputSize+1.

Bit width of each signed I / Q input sample. Range 4 to 32, default 16. The output width is InputSize + 1.

Default: 16

Options: 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Output Width OutputWidth

Max = InputSize+1 (full precision, holds the carry). Same as input = InputSize (no growth along a chain; the result is SATURATED if it exceeds the input range).

Default: Max (In+1)

Options: Max (In+1) Same as input

Usage

Bit widths

Data is signed two’s complement.

  • A_I, A_Q, B_I, B_Q : signed InputSize bits.
  • OUT_I, OUT_Q : signed InputSize + 1 bits.

The extra output bit holds the carry of the worst-case sum (+full_scale + full_scale), so the result is always exact. Truncate or round downstream if you need to return to InputSize bits.

Latency and throughput

  • #pragma HLS PIPELINE II=1 : one sample pair per clock.
  • 1-clock latency.
  • All data ports use the ap_none interface (no ready/valid handshake); the core is free-running (ap_ctrl_none).

Reset

RESET is the HLS synchronous reset (ap_rst).

Typical applications

  • Summing junction for combining two baseband paths (e.g. adding a correction / feedback term to a signal).
  • Beam-forming : coherent sum of two complex channels.
  • Complex accumulate stage when paired with a register / delay.

Resources & Timing

  • Latency: 1 clock cycle

  • Throughput: 1 sample per clock (II=1)

No multipliers or DSPs: two adders only. Implemented with Vitis HLS. Free-running core (ap_ctrl_none), no handshake logic.