Xilinx
HLS
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Introduction

The Complex Magnitude Approx block estimates the linear magnitude (envelope) of the complex input A = IN_I + j*IN_Q without a square root and without a multiplier. It uses the classic alpha-max-plus-beta-min identity:

      |A| = sqrt(I^2 + Q^2) ~= alpha * max(|I|,|Q|) + beta * min(|I|,|Q|)

The ideal min-worst-case coefficients are alpha = 0.947, beta = 0.393 (~4% peak error). To stay multiplier-free this block uses power-of-two friendly coefficients implemented with shift-and-add:

      15/16 * max = max - (max >> 4)          (alpha = 0.9375)
    15/32 * min = (min >> 1) - (min >> 5)   (beta  = 0.46875)
    |A| ~= 15/16*max + 15/32*min

This choice gives about 2% worst-case error at zero DSP cost. For an exact power figure use Component_ComplexMagSq (|A|^2); for a true magnitude use Component_ComplexAtan2 (CORDIC).

Pin Description

IN_I Input InputSize bit BIT VECTOR
In-phase (I) input sample. Signed, Input Bit Width bits.
Default: Must be connected
IN_Q Input InputSize bit BIT VECTOR
Quadrature (Q) input sample. Signed, Input Bit Width bits. Tie to zero to get |IN_I| of a real signal.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
HLS synchronous reset (ap_rst). Default: Global reset.
Default: Default Board Reset
MAG Output InputSize + 2 bit BIT VECTOR
Approximate linear magnitude |A|. Unsigned, InputSize + 2 bits.

Properties

Property window

Input Bit Width InputSize

Bit width of each I/Q sample (signed).

Bit width of each signed I / Q input sample. Range 4 to 32, default 16. Output width is InputSize + 2.

Default: 16

Options: 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Output Width OutputWidth

Extended = InputSize+2 (headroom, matches the other complex ops). Same as input = InputSize (no growth along a chain). The magnitude max is 0.703*2^InputSize so it always fits the input width UNSIGNED - ‘Same as input’ is lossless.

Default: Extended (In+2)

Options: Extended (In+2) Same as input

Usage

Algorithm 

      ai = |IN_I|
    aq = |IN_Q|
    mx = max(ai, aq)
    mn = min(ai, aq)
    MAG = (mx - (mx >> 4)) + ((mn >> 1) - (mn >> 5))

Taking max/min of the absolute values restricts the vector to a 45-deg wedge where the linear combination best approximates the Euclidean norm. The error oscillates between roughly 0% and +2% over angle; it is a slight over-estimate on average.

Bit widths

Inputs are signed; the internal absolute values and the output are unsigned (magnitude is non-negative).

  • IN_I, IN_Q : signed InputSize bits.
  • internal |I|, |Q| : unsigned InputSize bits.
  • MAG : unsigned InputSize + 2 bits.

Two guard bits are added because alpha*max + beta*min can exceed the InputSize-bit range of a single channel (the sum of the two weighted terms is up to ~1.4x the larger input). With the default InputSize = 16 the output is 18 bits.

Accuracy vs. alternatives 

      block                 error        cost
    complex_mag_approx    ~2% (|A|)    shifts + adds, 0 DSP
    complex_atan2 (mag)   exact*       CORDIC, adders, N_ITER clocks
    complex_magsq         exact (|A|^2) 2 DSP

(*atan2 magnitude carries the fixed 1.647x CORDIC gain.)

Latency and throughput

  • #pragma HLS PIPELINE II=1 : one result per clock.
  • 1-clock latency.
  • All ports use the ap_none interface (no ready/valid handshake).

Reset

RESET is the HLS synchronous reset (ap_rst); it clears the output register.

Typical applications

  • Envelope detector for an AM signal or a modulated pulse.
  • RSSI / signal-present indicator where ~2% error is fine.
  • AGC magnitude feedback term (cheaper than a CORDIC).

Resources & Timing

  • Latency: 1 clock cycle

  • Throughput: 1 sample per clock (II=1)

No multiplier and no square root: two absolute-value units, a compare/select for max/min, and four shift-and-add terms. Worst-case magnitude error ~2%. Fully pipelined.