Xilinx
Block Preview

Introduction

The block converts IEEE-754 floating-point values to fixed-point integer format, enabling integration between floating-point algorithms and fixed-point hardware implementations. On every rising edge of CLK, if CE = 1, the converter performs

$$ \mathrm{A}(n) = \text{fixed}(\mathrm{F}(n)), $$

where the input F follows IEEE-754 single or double precision format, and the output A is a custom fixed-point format with user-defined integer and fractional bit widths.

The conversion is implemented with the Xilinx floating_point IP core configured for float_to_fixed operation with blocking flow control and a fixed 7-cycle latency.

Pin Description

F Input Variable bit BIT VECTOR
Floating-point input value (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Precision selected by Float Format property.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable (tvalid), active high. When CE = 1, input F is accepted and conversion begins. Can be tied to ‘1’ for continuous operation.
Default: 1
READY_IN Input 1 bit BIT
Downstream ready signal (tready input), active high. Indicates if downstream logic can accept new data. Can be tied to ‘1’ if backpressure is not needed.
CLK Input 1 bit BIT
Global clock. Every rising edge triggers pipeline advancement. Connected to system acquisition clock.
Default: Default Board Clock
A Output 32 bit BIT VECTOR
Fixed-point output value. Width: Integer part n-bit + Fractional part n-bit (configurable 0-64 each). Signed integer representing the quantized floating-point value. Valid when DV = 1.
DV Output 1 bit BIT
Data Valid output (tvalid), active high. Indicates when output A contains valid converted data. Asserts 7 clock cycles after corresponding CE = 1.
READY_OUT Output 1 bit BIT
Upstream ready signal (tready output), active high. Indicates this block can accept new input data. Used for flow control in streaming pipelines.

Properties

Property window

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Input floating-point precision:

  • Single → 32-bit (8-bit exponent, 24-bit mantissa including implicit bit)
  • Double → 64-bit (11-bit exponent, 53-bit mantissa including implicit bit)

Single precision provides ~7 decimal digits; Double provides ~16 decimal digits.

Default: Single

Options: Single Double

Integer part n-bit IntLength

Number of bits in the integer part of the input

Number of bits in the integer part of the fixed-point output. Range: 0 - 64. Determines the maximum integer magnitude that can be represented. Total output width = IntLength + FractLength.

Default: 32

Range: 0 – 64

Fractional part n-bit FractLength

Number of bits in the factional part of the input

Number of bits in the fractional part of the fixed-point output. Range: 0 - 64. Determines the precision of fractional values in the output. The output represents values with resolution $2^{-\text{FractLength}}$.

Default: 0

Range: 0 – 64

Functional description

The component converts floating-point input to fixed-point output:

$$ A = \text{round}\left(F \times 2^{F_{\text{bits}}}\right), $$

where:

  • F → input floating-point value (IEEE-754)
  • A → output fixed-point value (signed integer)
  • $F_{\text{bits}}$ → Fractional part n-bit property

The total output width is Integer part n-bit + Fractional part n-bit.

Overflow/Underflow: Values exceeding the representable range will saturate or wrap according to the Xilinx IP core configuration.

IEEE-754 Input Format

Accepts standard IEEE-754 encoded values:

Single precision (32-bit):

  • 1 sign bit
  • 8 exponent bits
  • 23 mantissa bits (24 with implicit leading 1)

Double precision (64-bit):

  • 1 sign bit
  • 11 exponent bits
  • 52 mantissa bits (53 with implicit leading 1)

Timing

The IP has a fixed 7-cycle pipeline latency:

Clock cycle Event
0 Input F presented with CE = 1
7 Output A valid with DV = 1

The READY_IN/READY_OUT handshake signals enable backpressure control for streaming applications.

Typical use cases

  • Converting floating-point algorithm results to fixed-point for DAC output
  • Interface between floating-point processing and fixed-point control logic
  • Quantization for fixed-point implementation prototyping
  • Data type conversion in mixed-precision pipelines