Programmable Right Shift [TM]

Introduction link

This block performs a programmable right shift operation on time-multiplexed (TM) data streams. Unlike fixed shift operations, the shift amount is dynamically controlled via the integer SHIFT input port, allowing runtime flexibility.

Each bit of the input is shifted right by the amount specified on the SHIFT port (0 to Max Shift). The vacant leftmost positions are filled with either:

• Zeros (logical shift, Preserve Sign = false)
• Sign bit (arithmetic shift, Preserve Sign = true)

The shift operation can be:

• Combinational (zero latency, Latch Output = false)
• Registered (1 clock cycle latency, Latch Output = true)

$$ \mathrm{OUT}(n) = \mathrm{IN}(n) \gg \mathrm{SHIFT}(n), $$

where SHIFT is the runtime-configurable shift amount. The TM Factor property determines how many parallel samples are processed per clock cycle.

Pin Description link

Properties link

Functional description link

The component implements a programmable barrel shifter (right shift) in VHDL, replicated N times (where N = TM Factor) to support time-multiplexed data streams.

For each TM phase, the operation is:

$$ y[i] = x[i] \gg s, $$

where:

• $x[i]$ → input sample at phase $i$
• $y[i]$ → output sample at phase $i$
• $s$ → shift amount from SHIFT input (0 to Max Shift)

Shift modes link

The Preserve Sign property determines the fill behavior:

• Preserve Sign = false (Logical shift):

  • Vacant MSBs filled with zeros
  • Equivalent to unsigned division: $y = \lfloor x / 2^s \rfloor$

• Preserve Sign = true (Arithmetic shift):

  • Vacant MSBs filled with the sign bit (MSB of input)
  • Preserves sign for two’s complement numbers
  • Equivalent to signed division: $y = \lfloor x / 2^s \rfloor$ (signed)

Dynamic shift control link

• SHIFT port: Integer input specifying the shift amount (range: 0 to Max Shift)
• Barrel shifter: Efficiently implements any shift from 0 to Max Shift
• Same width: Output width always equals input width

Latency modes link

The block offers two latency configurations via the Latch Output property:

• Latch Output = false (default):

  • Purely combinational logic
  • Latency = 0 clock cycles
  • Output changes immediately with inputs

• Latch Output = true:

  • Output is registered (latched) on CLK rising edge
  • Latency = 1 clock cycle
  • Provides timing closure for high-speed designs
  • RESET clears the output register

Example (Logical shift) link

Given an 8-bit input and Max Shift = 4, Preserve Sign = false:

• Input = 11010110, SHIFT = 0 → Output = 11010110 (no shift)
• Input = 11010110, SHIFT = 2 → Output = 00110101 (shift right 2, zero-fill)
• Input = 11010110, SHIFT = 4 → Output = 00001101 (shift right 4)

Example (Arithmetic shift) link

Given an 8-bit input and Max Shift = 4, Preserve Sign = true:

• Input = 11010110 (negative), SHIFT = 2 → Output = 11110101 (sign-extended)
• Input = 01010110 (positive), SHIFT = 2 → Output = 00010101 (zero-filled)

Mathematical background link

• Logical shift: $x \gg s = \lfloor x / 2^s \rfloor$ (unsigned division)
• Arithmetic shift: $x \gg_{\text{arith}} s = \lfloor x / 2^s \rfloor$ (signed division, two’s complement)

This is commonly used for:

• Dynamic scaling and attenuation in signal processing
• Runtime-configurable division by powers of 2
• Adaptive fixed-point arithmetic
• Building configurable DSP and arithmetic pipelines

Timing link

The component latency depends on the Latch Output property:

All TM phases are processed in parallel within the same clock cycle.

Typical use cases link

• Variable-gain attenuation (divide by 2^N)
• Adaptive fixed-point rescaling
• Dynamic bit field extraction with configurable alignment
• Building configurable DSP pipelines
• Barrel shifter components in ALUs

Waveform example link

Example with TM Factor = 4, Max Shift = 4, Input = 4-bit values, SHIFT = 2, Preserve Sign = false, Latch Output = false.

Note: With Latch Output = false, output is immediate (combinational). Values in hex: 0xC » 2 = 0x3, 0xF » 2 = 0x3, 0xA » 2 = 0x2, 0x7 » 2 = 0x1.