ISIS PSD TM

Introduction link

Principle of Operation link

ISIS PSD TM is a Vitis HLS core (isispsd.cpp) generated and synthesised by the compiler for every distinct parameter set. It is a time-multiplexed block: the DATA pin carries TM = 4 samples of 16 bit in one 64-bit word per clock, so on the NI DAQ121 (acquisition clock CLK_ACQ = 250 MHz) the block processes 1 Gsample/s.

The block splits the stream in two paths:

• a trigger path that works on the average of the four samples of the clock, turns it into a rectangular discriminator pulse and shapes that pulse with two cascaded IIR filters. The width of the shaped pulse is what discriminates one particle species from another (the classic pulse shape discrimination);
• an integration path that works on the raw four lanes after a programmable delay, so that the charge integration can start before the sample that fired the trigger.

   DATA[63:0]  = lane3 | lane2 | lane1 | lane0      (lane0 = bits 15..0 = oldest sample)
      |
      |--> per lane:  x_i = lane_i - OFFSET , negated when POLARITY = 1
      |      |
      |      +--> data16 = (x0+x1+x2+x3) >> 2  ---> compare with TH ---> MON_DISCR
      |                                                    |
      |                                     low-pass IIR --+--> MON_LP
      |                                                    |
      |                                     high-pass IIR -+--> MON_HP --> compare TH_PSD
      |                                                                          |
      |                                          OVR_SAMPLES consecutive clocks --+
      |                                                                          |
      +--> 128-word delay line (PRETRG clocks) --> d0..d3 ---------------> integrate
  

The energy of an event is the sum of the four delayed lanes accumulated over INT_SP clocks:

$$ \mathrm{EVNT_INT} ;=; \sum_{n=0}^{\mathrm{INT_SP}-1};\sum_{i=0}^{3} d_i[n] $$

and the peak is the largest single sample seen inside that window:

$$ \mathrm{EVNT_PEAK} ;=; \max_{n,i}; d_i[n] $$

Because INT_SP and PRETRG are counted in clock cycles, every unit is worth TM = 4 samples (4 ns at 250 MHz).

Pin Description link

Properties link

⚙️ Detailed Operation link

Lane unpacking and the TM factor link

The symbol pin DATA is declared TYPE_STD_LOGIC_VECTOR_TM, 16 bit wide, with TimeMultiplexed = 4; the HDL pad that is actually generated is a plain 64-bit port named data. Following the repo-wide TM convention, lane 0 lives in the low bits and is the oldest sample of the clock. The core unpacks it as

  datax_0 = (data >>  0) & 0xFFFF;   // oldest
datax_1 = (data >> 16) & 0xFFFF;
datax_2 = (data >> 32) & 0xFFFF;
datax_3 = (data >> 48) & 0xFFFF;   // newest
  

Each lane has OFFSET subtracted and is negated when POLARITY = 1 (x = -(lane - OFFSET)), so OFFSET is the pedestal of the digitiser and POLARITY makes negative-going pulses positive.

The Time Mux property only offers the value 4 — the core is hard-wired to four lanes (data is 64 bit, the timestamp advances by 4 per clock, the integrator adds four terms).

Trigger path link

1. Lane average. data16 = (x0 + x1 + x2 + x3) >> 2 — the mean of the four samples of the clock. This is the only signal compared against TH; the block therefore triggers on a 250 MHz decimated version of the 1 GS/s stream.

2. Discriminator. MON_DISCR is a rectangular pulse: data16 > TH ? 6553 : 0, where 6553 = (int)(0.2 × 0x7FFF). Its width carries the pulse-shape information.

3. Low-pass section — a 2nd-order IIR written in scattered look-ahead form, which is what lets Vitis close II = 1 at 4 ns:

   $$ y[n] ;=; \sum_{k=0}^{6} b_k,x[n-k] ;-; a_1,y[n-3] ;-; a_2,y[n-6] $$

   with the coefficients compiled into isispsd.cpp:

   coefficient	value
   $a_1$	-1.691126416184245
   $a_2$	0.7213785295739619
   $b_0 \dots b_6$	0.00093575, 0.00364298, 0.00699309, 0.00838898, 0.00644455, 0.00309409, 0.00075267

   The result is exported on MON_LP.

4. High-pass section — same idea, 4 feed-forward taps and one feedback tap at $n-3$:

   $$ y[n] ;=; \sum_{k=0}^{3} b_k,x[n-k] ;-; a_1,y[n-3] $$

   coefficient	value
   $a_1$	-0.8599680957679054
   $b_0 \dots b_3$	0.97547839, -0.0478406, -0.04549434, -0.88214345

   The result is exported on MON_HP.

   Coefficients are stored as ap_fixed<18,2> (2 integer bits, 16 fractional bits) and the filter states as ap_fixed<24,16>.

5. PSD decision. While MON_HP > TH_PSD, FLAG_TH_PSD is high and an internal counter runs. When that counter becomes strictly greater than OVR_SAMPLES (and the previous crossing has been released), FLAG_THN_PSD pulses for one clock and an integrator slot is armed. Dropping below TH_PSD for a single clock resets the counter to zero, so the OVR_SAMPLES clocks must be consecutive.

Integration path and the pre-trigger delay line link

The raw 64-bit word is pushed into a 128-entry circular delay line (one entry = one clock = 4 samples) and read back PRETRG clocks later:

  delay1[write_pointer1] = data;
read_pointer1 = write_pointer1 - (int)offset_samples;   // offset_samples = PRETRG
if (read_pointer1 < 0) read_pointer1 += 128;
  

Four parallel integrators (PARALLEL_INTEGRATOR = 4) are available. When an event is armed, the first slot that is neither integrating nor waiting to be committed is taken; its accumulator, sample counter and peak register are cleared and its start timestamp is latched. While a slot is running it adds the four delayed lanes every clock and keeps the maximum of the four lanes:

  p_integral[i] += datad_0 + datad_1 + datad_2 + datad_3;   // one clock = 4 samples
if (datad_max > p_maxv[i]) p_maxv[i] = datad_max;
  

After INT_SP clocks the slot stops and is marked to be committed.

Pile-up handling (Pileup property) link

The allocation loop walks the slots from 0 upwards; every busy slot it passes before finding a free one has its peak-running flag cleared. What that means depends on the property, which is injected as a #define at the top of the generated .cpp:

FLAG_PEAK exports the per-slot peak-running bitmap, so FLAG_INT and FLAG_PEAK differ exactly on the slots that have been hit by a pile-up.

Event output link

Committed slots are drained with a fixed priority (slot 0 first, then 1, 2, 3), at most one event per clock. On that clock EVNT_VALID is high for one cycle and EVNT_TS, EVNT_INT, EVNT_PEAK and EVNT_RATIO are valid.

The internal timestamp counts samples: it is incremented by 4 on every clock and cleared to 0 while T0 is high. The value latched when the event is armed is

$$ \mathrm{EVNT_TS} ;=; t_{\text{sample}} ;+; 4\cdot\mathrm{PRETRG} $$

(the core computes timestamp - ((0 - offset_samples) << 2), i.e. it adds four times the pre-trigger; the sign is as written in the source).

EVNT_RATIO depends on the Ratio property:

Monitor outputs link

MON_INT / MON_PEAK are not an event stream — they follow slot 0 and are meaningless while slot 0 is idle.

Generated hardware, clock and build link

• CompileHDL writes HLS/<unique>/isispsd.cpp (with the #defines prepended) and a hls_compile.tcl that runs csynth_design with set_directive_top -name <unique> isispsd, targeting the project FPGA part and a clock period of floor(1000000 / AcquisitionClockFreq) ns — 4 ns on the NI DAQ121, whose CLK_ACQ is 250 MHz. All generated VHDL is merged into HDL/pcores/<unique>.vhd.
• The IP name is isispsd_<8 letters> where the letters are an MD5 of (component name, ADC BITS, Time Mux, Ratio).
• The core is free-running: #pragma HLS PIPELINE II=1 and #pragma HLS INTERFACE ap_ctrl_none port=return, so there is no start/done handshake. ap_clk is tied to the project acquisition clock automatically — there is no CLK pin on the symbol — and ap_rst to the project global reset when RESET is left open.

There is no CompileMMC / CompileSDK content: the block exposes no software registers. Everything is configured through pins, so use constant blocks or a register block to drive TH, TH_PSD, OVR_SAMPLES, PRETRG and INT_SP.

Resources & Timing link

• Latency: Declared block latency: 20 clocks with Ratio = External, 55 clocks with Ratio = Internal

• Throughput: One 64-bit word (4 samples) per clock, II = 1; at most one event per clock on EVNT_VALID

• 4 concurrent integrators (PARALLEL_INTEGRATOR = 4); a 5th simultaneous event is dropped.
• 128-entry × 64-bit pre-trigger delay line.
• Filter coefficients are ap_fixed<18,2>, filter states ap_fixed<24,16>.
• Synthesised for a clock period of floor(1000000 / AcquisitionClockFreq) ns (4 ns on the NI DAQ121, 250 MHz); LUT/DSP/BRAM figures are whatever Vitis reports for that run and are not fixed by the source.