RF Sequential FIR (fixed coefs)

Introduction link

The Sequential FIR (fixed coefs) block computes a standard FIR

      y[n] = sum_{k=0..NumTaps-1} h[k] * x[n-k]
  

but instead of laying down NumTaps parallel multipliers it uses one time-shared MAC that walks the taps one per system-clock cycle. This is the natural architecture when the data rate is far below the system clock: the block accepts one input sample every ClockRatio system clocks (a “gapped” stream), and it has that whole window to sweep the MAC across every tap.

The block uses a custom WebView2 graphical designer (the FIR Designer, shown above) instead of the standard property grid. Double-clicking the block opens the designer, where you specify the response (low-pass / high-pass / band-pass / band-stop, window or equiripple method, cut-off / transition / attenuation), see the live magnitude response and pole/zero-free tap stem plot, pick the hardware widths and the SysClk / DataClk ratio, and read off the resource / timing estimate. On Save & Close the designer writes the quantised integer coefficients and the hardware parameters back into the block; they are baked into the generated HLS at synthesis time and are not exposed to the fabric.

      SAMPLE_IN  ┐  (1 pulse per new input sample, gapped every ClockRatio)
    IN_I / IN  ┤ [ 1x time-shared MAC over NumTaps ] ── OUT_I / OUT
    IN_Q       ┘                                     └─ OUT_Q
                                        VALID_OUT ── (pulse when result ready)
               (h[k] baked in by the FIR Designer)
  

For a run-time reloadable version see Component_SeqFIRProgrammable (seq_fir_prog). For a fully-parallel (one-multiplier-per-tap, II=1 at the full clock) filter see Component_FIR (fir).

Pin Description link

Properties link

Usage link

Time-sharing / clock-ratio concept link

A conventional direct-form FIR needs NumTaps DSP multipliers because it finishes a full convolution every clock. When the data is slow relative to the fabric clock, that is wasteful: the multipliers sit idle most of the time. The sequential FIR instead uses the idle cycles.

• CLK runs at the system clock (SysClk, typically the acquisition clock).
• A new input sample is presented only once every ClockRatio system clocks. SAMPLE_IN is pulsed high for one SysClk cycle to mark it; the sample rate is DataClk = SysClk / ClockRatio.
• On the SAMPLE_IN pulse the block shifts the new sample into the delay line, clears the accumulator and starts a counter.
• On each following SysClk cycle it performs exactly one MAC: acc += delay[cnt] * h[cnt], incrementing cnt.
• After NumTaps cycles the accumulation is complete: the block right- shifts the accumulator, drives the result on OUT and pulses VALID_OUT for one cycle.

Because one tap is processed per system clock, the whole sweep must fit inside the inter-sample window:

      NumTaps <= ClockRatio          (checked at compile time)
  

If NumTaps > ClockRatio the compile fails with an error asking you to raise ClockRatio or lower NumTaps. The MAC therefore needs only one multiplier (real) or two (complex I/Q), independent of the filter length — the cost is throughput, not area.

Bit widths and scaling link

Data is signed two’s complement. Internally:

      ACC_SIZE = InputSize + CoefSize + 8            (8 guard bits)
    OUT_SIZE = ACC_SIZE - CoefShift
             = InputSize + CoefSize + 8 - CoefShift
  

The 8 guard bits let the accumulator sum up to 256 taps without overflow. CoefShift is the right-shift applied to the accumulator to restore unity DC gain; the FIR Designer stores the exact shift it used when quantising (shift in the project JSON). When absent it defaults to CoefSize - 1, in which case OUT_SIZE = InputSize + 9.

Complex vs real link

• Real: one channel — pins IN / OUT, one multiplier.
• Complex: independent I and Q sharing the same real coefficient set — pins IN_I/IN_Q and OUT_I/OUT_Q, two multipliers. This is the usual case after a complex mixer.

Coefficient generation (FIR Designer) link

The designer quantises the floating-point prototype h_float[k] to a signed CoefSize-bit integer array h_int[k] with a scale of 2^(CoefSize-1) - 1, records the tap count (n_taps) and the accumulator shift (shift), and stores everything as JSON in the hidden FIRProject property. The HLS side reads h_int directly into a compile-time ROM, so Vivado can prune zero / trivial coefficients.

Visual designer link

This block has no plain property grid. Every parameter — signal type, input / coefficient widths, tap count, SysClk / DataClk ratio and the filter response itself — is edited inside the FIR Designer that opens on double-click (see the screenshot in the introduction). The designer offers a MATLAB-like workflow: choose the filter template, tune the frequency spec, watch the magnitude response and tap plot update live, and check the estimated multiplier count and MAC latency before pressing Save & Close. The hidden FIRProject property carries the resulting spec + coefficients; the visible hardware properties documented below are mirrored from the designer so that symbol drawing and HDL generation keep working off ordinary property values.

Latency and throughput link

• #pragma HLS PIPELINE II=1: the core advances one MAC per system clock.
• End-to-end latency from SAMPLE_IN to VALID_OUT is about NumTaps system clocks (one per tap).
• Sustained throughput is one filtered sample every ClockRatio system clocks, i.e. the input DataClk rate.
• All ports use the ap_none interface (no ready/valid handshake beyond SAMPLE_IN / VALID_OUT).

Reset link

RESET is the HLS synchronous reset (ap_rst): it clears the delay line, the accumulator and the tap counter.

Typical applications link

• Long channel-select filter on an already-decimated stream where a parallel FIR would burn hundreds of DSPs.
• Sharp baseband LPF after a CIC / halfband decimator.
• Pulse-shaping / matched filter at a low symbol rate.

Resources & Timing link

• Latency: ~NumTaps system-clock cycles from SAMPLE_IN to VALID_OUT

• Throughput: One sample every ClockRatio system clocks (the DataClk rate)

Implemented with Vitis HLS. Only one DSP multiplier for Real, two for Complex I/Q, regardless of filter length — the MAC is time-shared across taps (one MAC per system clock, II=1). Compile-time constant coefficients let Vivado prune zero / trivial taps. A delay line of NumTaps samples (per channel) is kept in registers / SRL. Hard constraint enforced at compile: NumTaps <= ClockRatio.