Xilinx
Block Preview

Introduction

The block computes $X[k] = \sum_n w[n],x[n],e^{-j2\pi kn/N}$ : each input sample is multiplied by a 16-bit Q16 window coefficient before entering a Xilinx xfft core (unscaled, natural order). Double-clicking the block opens the FFT Windowed Designer: choose the window family (and its parameter - Kaiser $\beta$, Gaussian $\sigma$, Tukey $\alpha$, Chebyshev/Taylor sidelobe level, DPSS NW), build a test signal from tones (frequency, amplitude, PHASE each) plus noise, and see the windowed waveform and the resulting spectrum (dB) against the rectangular reference. The panel also shows the resource estimate and the timing constraints of the chosen configuration.

Pin Description

DATA_IN Input 16 bit BIT VECTOR
16-bit signed time-domain samples, CE gated.
Default: Must be connected
CE Input 1 bit BIT
Clock enable. Keep the duty <= hop/N with overlap. Default ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
OUT_RE Output 32 bit BIT VECTOR
Real part of the spectrum bins (sequential burst, 32 bit).
OUT_IM Output 32 bit BIT VECTOR
Imaginary part of the spectrum bins.
DV Output 1 bit BIT
Bin valid.
FIRST Output 1 bit BIT
Pulse on bin 0 of each frame.
LAST Output 1 bit BIT
Pulse on bin N-1 of each frame.
BUSY Output 1 bit BIT
A frame is being fed or transformed.
OVERRUN Output 1 bit BIT
One-cycle pulse when a frame boundary is missed (input too fast for the configuration).
START
Burst engines only: begins a frame (tie to 1 for auto restart every hop samples). Not present with Pipelined.

Properties

Property window

FFT Length Length

Transform length N (power of 2)

Transform length N (128..16384, power of 2).

Default: 1024

Options: 128 256 512 1024 2048 4096 8192 16384

Algorithm Algorithm

Pipelined: continuous, no START pin, frames free-run every hop samples. Radix-4/Radix-2/Radix-2 Lite: framed, needs START (tie to ‘1’ for auto restart).

Pipelined (continuous, no START) or Radix-4 / Radix-2 / Radix-2 Lite burst engines (framed, START required). Same area/speed trade-offs as the FFT block.

Default: Pipelined

Options: Pipelined Radix-4 Radix-2 Radix-2 Lite

Overlap Overlap

Frame overlap. None: 1 core. 25% (hop=3N/4) or 50% (hop=N/2): TWO xfft cores in ping-pong. Max input CE duty = hop/N.

None / 25% / 50%. Overlap instantiates two xfft cores automatically and limits the input CE duty to hop/N.

Default: None

Options: None 25% 50%

Window Window

Window family (set by the designer, double-click the block)

Window family - set from the designer (double click).

Default: Hann

Config (JSON, use designer) WFProject

Designer state incl. window coefficients (Q16)

Continuous vs framed operation

  • Pipelined engine: NO START pin. The block processes continuously: a new frame begins automatically every hop = N - overlap samples and spectra stream out back to back.
  • Radix-4 / Radix-2 / Radix-2 Lite: the FFT is framed, not continuous - the START pin begins a frame (bin 0 = the START sample). Tie START to ‘1’ to restart automatically every hop samples. The designer reminds you of this.

Overlap

With overlap 25% (hop = 3N/4) or 50% (hop = N/2) TWO xfft cores are instantiated automatically in ping-pong: every incoming sample feeds up to two active frames with different window phases (no history buffer). Output bursts are serialized in strict frame order; a per-core elastic FIFO absorbs the backpressure. The input CE duty must not exceed hop/N (100% / 75% / 50%): a missed frame boundary raises a one-cycle OVERRUN pulse and the scheduler retries.

Verified in simulation (N=256, Hann, 50% overlap, CE duty 50%, two-tone signal): 41 consecutive overlapping frames all match the numpy windowed FFT within 6e-5, zero overruns.

Outputs

Sequential complex bins on OUT_RE / OUT_IM (32 bit, unscaled full precision = 16 + log2 N + 1 bits), DV per bin, FIRST / LAST frame markers, BUSY, OVERRUN.

Coefficient export

The designer’s Export CSV button saves the Q16 coefficients (addr,coef per line) to load at runtime into the FFT Windowed Prog variant through its COEF_ADDR / COEF_DATA / COEF_WE bus.