X2730 Digitizer
Waveform readout block for the X2730 board. Uses the high-speed DMA engine and DDR4 memory to capture and transfer time-multiplexed waveforms to the PC. All channels are acquired synchronously on trigger.
Introduction
The X2730 Digitizer block implements waveform readout using the high-speed DMA engine and the large DDR4 memory buffer inside the board. This block takes time-multiplexed (TM) signal vectors and, upon trigger, acquires and transfers them to the PC.
All acquisition parameters are configured by software using CAEN FELib or the SciCompiler-generated SDK. The acquisition is initialized by a LOW → HIGH transition of the TRIGGER input (except when software trigger is selected).
Important: The acquisition of all 32 channels is always synchronous - when the trigger fires, all channels are captured at the same instant.
Time multiplexing: the board has 32 channels sampling at 500 MS/s, and that is why every ANx input is a time-multiplexed 16-bit port with a TM factor of 4 - it carries 4 samples = 64 bits per clock cycle.
At a glance:
| Channels | 32 |
| Sampling rate per channel | 500 MS/s |
| TM factor | 4 (four samples per clock) |
| Bits per clock per channel | 64 |
| Symbol pins | AN0-AN31, CE, TRIGGER |
| Properties | none |
Pin Description
Channel Enable for per-sample decimation.
- HIGH: Current sample is captured
- LOW: Current sample is discarded
- Unconnected: All samples captured (forced to ‘1’)
Must be enabled in the property box to appear on the symbol. Useful for reducing data rate or conditional sampling.
Acquisition trigger input. A LOW → HIGH transition starts the waveform readout process.
Important: The acquisition of all 32 channels is always synchronous. When trigger fires, all channels are captured at the same instant.
If software trigger is enabled via CAEN FELib, this pin can be left unconnected.
Time-multiplexed waveform input channels (32 total). Each channel carries 4 time-multiplexed 16-bit samples per clock, i.e. 64 bits per clock cycle (TM factor 4).
Connect to ADC outputs or processing chain outputs. Unconnected channels are automatically forced to 0.
Properties
Usage
What the Digitizer Does
The Digitizer is NOT the ADC itself - it is the readout block that:
- Receives time-multiplexed waveform data from the analog inputs or processing chains
- Captures all 32 channels simultaneously when triggered
- Stores the waveforms in the DDR4 memory buffer
- Transfers the data to the PC via high-speed DMA
┌─────────────────────────────────────────────────────────────────┐
│ Digitizer Flow │
│ │
│ TM Signals ──►┌──────────────┐ ┌─────────┐ ┌─────┐ │
│ (32 ch) │ │ │ │ │ │ │
│ ══════════════│ DIGITIZER │════►│ DDR4 │════►│ DMA │═══╋══► PC
│ │ │ │ Buffer │ │ │ │
│ TRIGGER ─────►│ │ │ │ │ │ │
│ └──────────────┘ └─────────┘ └─────┘ │
│ ▲ │
│ │ │
│ L→H starts acquisition │
└─────────────────────────────────────────────────────────────────┘
Synchronous Acquisition
All 32 channels are acquired synchronously. When the TRIGGER signal transitions from LOW to HIGH:
- All channel inputs are sampled at the same clock edge
- The acquisition continues for the configured record length
- Data is buffered in DDR4 for transfer to PC
This ensures perfect time alignment between channels for multi-channel analysis.
Time-Multiplexed Inputs
The Digitizer accepts time-multiplexed (TM) inputs. Each 16-bit ANx pin carries 4 consecutive samples per clock cycle:
X2730 (TM Factor = 4):
┌─────────────────────────────────────────────────┐
│ Clock Cycle N │
├───────────┬───────────┬───────────┬───────────┤
│ Sample 0 │ Sample 1 │ Sample 2 │ Sample 3 │
│ (16-bit) │ (16-bit) │ (16-bit) │ (16-bit) │
└───────────┴───────────┴───────────┴───────────┘
Total: 64 bits per clock per channel
Every block you connect upstream of the Digitizer must therefore be a TM block with the same TM factor. Connecting a plain 16-bit signal to an ANx pin is a size mismatch, not a decimation.
Typical Usage
Connect the Digitizer to receive waveforms from the analog inputs or processing chain outputs:
┌──────────────┐ ┌──────────────┐
│ Board │ │ X2730 │
│ Analog │ (or processing) │ Digitizer │
│ Inputs │ │ │
├──────────────┤ ├──────────────┤
│ ADC_CH0 ─────┼────────────────────────►│ AN0 │
│ ADC_CH1 ─────┼────────────────────────►│ AN1 │
│ ... │ │ ... │
│ ADC_CH31 ────┼────────────────────────►│ AN31 │
│ │ │ │
│ │ Trigger logic ──────►│ TRIGGER │
└──────────────┘ └──────────────┘
Channel Enable (CE) Pin
The optional CE (Channel Enable) pin allows per-sample data decimation:
| CE State | Behavior |
|---|---|
| HIGH | Sample is captured and stored |
| LOW | Sample is discarded |
| Unconnected | All samples captured (CE forced to ‘1’) |
Use cases for CE:
- Reduce data rate by decimating samples
- Conditional sampling based on external logic
- Synchronize with external timing signals
Best Practices
- All channels synchronous: Remember that trigger affects all 32 channels simultaneously
- Unconnected channels: Channels without connections are forced to 0
- Trigger timing: Ensure trigger arrives when signals are stable
- CE usage: Use CE for decimation only when needed
- Buffer management: Monitor DDR4 buffer to avoid overflow
Resources & Timing
-
Latency: 1 clock cycle for trigger detection
-
Throughput: 32 channels × 4 samples per clock
- X2730: 32 × 4 = 128 samples per clock cycle (2048 bits)
- Data is buffered in DDR4 before DMA transfer to PC
- All channels acquired synchronously on trigger edge
Supported Boards
- X2730