TM
Block Preview

Introduction

This block packs multiple independent scalar signals into a single time-multiplexed (TM) bus. It is used to combine parallel data streams into a compact TM representation for efficient processing.

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT}[W \times (i+1) - 1 : W \times i] = \mathrm{TM}_i, \quad i = 0 \ldots N-1 $$

where $W$ is the word size and $N$ is the TM factor.

Pin Description

TM_0 Input 16 bit BIT VECTOR
TM_1 Input 16 bit BIT VECTOR
TM_2 Input 16 bit BIT VECTOR
TM_3 Input 16 bit BIT VECTOR
OUT Output Variable bit TM

Output TM bus, always TM. Width: Word Size × TM Factor TM Factor: Configurable (2 to 32)

Bit layout: OUT[(i+1)×W-1 : i×W] = TM_i Output is combinational (zero latency).

TM_0 ... TM_{N-1} Variable bit

N independent scalar input signals (where N = TM Factor). Each input: std_logic_vector of width = Word Size Pin names: TM_0, TM_1, TM_2, …, TM_{N-1}

All inputs must be connected for successful compilation.

Default: Must be connected

Properties

Property window

Word Size InputWordsize

Set the size in bit of word in the input/output

Width in bits of each input signal (1 to 16384 bits). All inputs must have this same width.

Default: 16

Range: 1 – 16384

TM Factor TMFactor

Select the TM Factor of the input

Number of TM phases (2 to 32). This determines how many input pins (TM_0 through TM_{N-1}) are created. Total output width = Word Size × TM Factor.

Default: 4

Options: 2 4 8 16 32

Functional description

The TM Packer concatenates N independent scalar inputs into a single TM bus. Each input signal becomes one phase of the output TM bus.

Packing operation

For a TM factor of $N$ and word size $W$:

$$ \mathrm{OUT} = \mathrm{TM}{N-1} ,||, \mathrm{TM}{N-2} ,||, \ldots ,||, \mathrm{TM}_1 ,||, \mathrm{TM}_0 $$

where $||$ denotes concatenation. In bit notation:

  • Phase 0 → bits $[W - 1 : 0]$
  • Phase 1 → bits $[2W - 1 : W]$
  • Phase $i$ → bits $[(i+1)W - 1 : iW]$
  • Phase N-1 → bits $[NW - 1 : (N-1)W]$

Total output width: $W \times N$ bits

Example with TM Factor = 4, Word Size = 16

Four 16-bit inputs packed into a 64-bit TM output:

  • TM_0 = 0x1234
  • TM_1 = 0x5678
  • TM_2 = 0x9ABC
  • TM_3 = 0xDEF0

Packed TM output (64 bits): $$ \mathrm{OUT}[63:0] = \texttt{0xDEF0_9ABC_5678_1234} $$

Bit layout:

  OUT[63:48] = 0xDEF0  (TM_3)
OUT[47:32] = 0x9ABC  (TM_2)
OUT[31:16] = 0x5678  (TM_1)
OUT[15:0]  = 0x1234  (TM_0)

Input requirements

  • All input signals must have the same width (Word Size property)
  • Number of inputs equals the TM Factor property
  • All inputs must be connected for successful compilation

Signal naming

The component creates N input pins named:

  • TM_0, TM_1, TM_2, …, TM_{N-1}

Each input pin is a scalar std_logic_vector of width $W$.

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
TM Packer 0

The TM output is available immediately in the same clock cycle as the inputs.

Typical use cases

  • Combining multiple ADC channels into a TM data stream
  • Creating TM buses for parallel processing pipelines
  • Interfacing scalar outputs to TM processing blocks
  • Data stream multiplexing for bandwidth optimization

Important notes

  • All inputs must be connected - compilation will fail if any TM_i input is unconnected
  • Input order matters: TM_0 becomes LSBs, TM_{N-1} becomes MSBs
  • No clock required - purely combinational wiring
  • Inverse operation: use TM Splitter to unpack