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Introduction

The Custom HDL (NEW) component is an advanced replacement for the legacy User HDL component. It features a modern Monaco Editor (the same editor used in VS Code), multi-file project support, VHDL generics, and integrated GHDL syntax checking.

Key features:

  • Monaco Editor: Professional code editing with syntax highlighting
  • Multi-file projects: Organize code across multiple HDL files
  • Generics support: Define and use VHDL generic parameters
  • GHDL integration: Real-time syntax checking and error reporting
  • Hierarchy view: Visualize component instantiation hierarchy
  • Auto-detection: Automatically detect ports and generics from HDL code

Pin Description

CLK 1 bit
Clock input signal. Connect to the system clock (typically CLK_ACQ). Ports marked as CLOCK function are connected here.
Default: Must be connected
RESET 1 bit
Active-high synchronous reset signal. Connect to the global reset. Ports marked as RESET function are connected here.
Default: Must be connected
Custom Ports Variable bit

User-defined ports as configured in the I/O Configuration panel.

Port types:

  • STD_LOGIC: Single bit
  • STD_LOGIC_VECTOR: Multi-bit bus (1-1024 bits)
  • STD_LOGIC_VECTOR_TM: Time-multiplexed vector
  • INTEGER: Integer type (converted to vector)

Port functions:

  • PORT: Standard data port
  • CLOCK: Clock signal (size must be 1)
  • RESET: Reset signal (size must be 1)

Properties

HDL Project Data HDLProject

JSON containing all project data (files, ports, generics)

JSON container for the entire project, including:

  • File contents (Base64 encoded)
  • Port definitions
  • Generic definitions
  • Project settings

This is automatically managed by the editor.

Top Entity TopEntity

Name of the top-level entity

Name of the top-level entity in your HDL project. This entity will be instantiated by SCI-Compiler.

The top entity:

  • Must exist in one of the project files
  • Port names must match I/O Configuration
  • Is marked with a star in the file explorer
Code Language CodeLanguage

HDL Language (VHDL or Verilog)

Default: VHDL

Options: VHDL Verilog

Language Language

HDL language selection.

Options:

  • VHDL: VHSIC Hardware Description Language
  • Verilog: Alternative HDL (limited support)

Functional description

The Custom HDL (NEW) component provides a complete development environment for creating custom HDL blocks within SCI-Compiler.

Custom HDL Editor

Editor interface

The editor interface consists of:

  • Toolbar: Save, Refresh, Check Syntax buttons
  • Explorer panel: File tree and I/O Configuration
  • Hierarchy panel: Design hierarchy visualization
  • Code editor: Monaco-based HDL editor
  • Problems panel: Syntax errors and warnings

Multi-file projects

Unlike the legacy component, Custom HDL (NEW) supports multiple HDL files:

  • Create a main top-level entity
  • Add sub-components in separate files
  • The hierarchy view shows how components are instantiated

Hierarchy View

I/O Configuration

The I/O Configuration panel allows you to define:

Ports:

Property Description
Name Port identifier (must match HDL)
Direction IN or OUT
Type STD_LOGIC, STD_LOGIC_VECTOR, INTEGER
Size Bit width (1-1024)
Function PORT, CLOCK, or RESET
Time Multiplexing TM factor (for TM signals)

Generics:

Property Description
Name Generic parameter name
Type INTEGER, NATURAL, POSITIVE, BOOLEAN, STRING
Default Default value
Description Documentation

Auto-detection

Click Scan HDL to automatically detect ports and generics from your HDL code. The parser analyzes the entity declaration and populates the I/O Configuration table.

Syntax checking

Click Check Syntax to run GHDL on your code. Errors and warnings appear in the Problems panel with:

  • File name
  • Line and column number
  • Error message
  • Click to navigate to the error location

Example VHDL with Generics

vhdl 
  library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity configurable_counter is
    Generic (
        WIDTH : INTEGER := 16;
        MAX_COUNT : INTEGER := 1000
    );
    Port (
        CLK    : in  STD_LOGIC;
        RESET  : in  STD_LOGIC;
        ENABLE : in  STD_LOGIC;
        COUNT  : out STD_LOGIC_VECTOR(WIDTH-1 downto 0);
        DONE   : out STD_LOGIC
    );
end configurable_counter;

architecture Behavioral of configurable_counter is
    signal counter : unsigned(WIDTH-1 downto 0) := (others => '0');
begin
    process(CLK)
    begin
        if rising_edge(CLK) then
            if RESET = '1' then
                counter <= (others => '0');
                DONE <= '0';
            elsif ENABLE = '1' then
                if counter = MAX_COUNT - 1 then
                    counter <= (others => '0');
                    DONE <= '1';
                else
                    counter <= counter + 1;
                    DONE <= '0';
                end if;
            end if;
        end if;
    end process;

    COUNT <= std_logic_vector(counter);
end Behavioral;

Hierarchy visualization

The Hierarchy panel shows the component instantiation tree:

  • Top entity marked with a star
  • Expandable/collapsible nodes
  • Click to open the corresponding file
  • Unresolved components shown in italics

Typical use cases

  • Complex custom logic: Multi-file designs with sub-components
  • Parameterized components: Using generics for configurable designs
  • IP integration: Importing existing VHDL/Verilog IP cores
  • Algorithm development: Prototyping with real-time syntax feedback

Migration from User HDL

To migrate from the legacy User HDL component:

  1. Create a new Custom HDL (NEW) component
  2. Copy your HDL code to a new file
  3. Re-define ports in I/O Configuration (or use Scan HDL)
  4. Add any required generic parameters
  5. Connect signals in the schematic