Xilinx
HLS
Block Preview

Introduction

The Complex -> Real block routes one of the two channels of a complex baseband sample to a single real output, chosen by the Component to Extract property:

      Select = "I" :  OUT[n] = IN_I[n]
    Select = "Q" :  OUT[n] = IN_Q[n]

The choice is baked in at synthesis time (#define SELECT), so no run-time mux is generated. Data is signed two’s complement and the width is unchanged.

Pin Description

IN_I Input InputSize bit BIT VECTOR
In-phase (I) input sample. Signed, Input Bit Width bits. Ignored when Select = “Q” but must still be connected.
Default: Must be connected
IN_Q Input InputSize bit BIT VECTOR
Quadrature (Q) input sample. Signed, Input Bit Width bits. Ignored when Select = “I” but must still be connected.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
HLS synchronous reset (ap_rst). Default: Global reset.
Default: Default Board Reset
OUT Output InputSize bit BIT VECTOR
Real output = IN_I (Select = “I”) or IN_Q (Select = “Q”). Signed, InputSize bits.

Properties

Property window

Input Bit Width InputSize

Bit width of each I/Q input sample.

Bit width of each signed I / Q input sample. Range 4 to 32, default 16. The real output uses the same width.

Default: 16

Options: 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Component to Extract Select

Which channel to route to OUT.

Which channel to route to OUT: “I” (in-phase, default) or “Q” (quadrature). Baked in at synthesis time; no run-time mux.

Default: I

Options: I Q

Usage

Bit widths

Data is signed two’s complement.

  • IN_I, IN_Q : signed InputSize bits.
  • OUT : signed InputSize bits (a copy of the selected channel).

Behaviour

This is the inverse type-adapter of Real -> Complex: it drops one channel of a complex stream so the remaining real component can feed a real-only block, a DAC, or a monitor. The unused input channel still has to be connected but is otherwise ignored. Changing Select does not trigger a redesign of surrounding logic (RedesignIfChanged = False), but it does change which HLS core is compiled.

Latency and throughput

  • #pragma HLS PIPELINE II=1 : one sample per clock.
  • 1-clock latency.
  • All data ports use the ap_none interface (no ready/valid handshake); the core is free-running (ap_ctrl_none).

Reset

RESET is the HLS synchronous reset (ap_rst).

Typical applications

  • Tap the in-phase (I) component of a down-converted signal for a real detector or DAC.
  • Tap the quadrature (Q) component for phase / imaginary-part monitoring.
  • Type adapter ahead of a real-only DSP block.

Resources & Timing

  • Latency: 1 clock cycle

  • Throughput: 1 sample per clock (II=1)

Zero DSPs: a single pass-through wire from the selected channel. Implemented with Vitis HLS. Free-running core (ap_ctrl_none), no handshake logic.