Block Preview

Introduction

This block converts a std_logic_vector binary signal to a VHDL INTEGER type. It allows you to interface between bit-level std_logic_vector signals and VHDL’s high-level INTEGER type for arithmetic operations.

The operation is purely combinational with zero clock latency:

$$ \mathrm{INT} = \mathrm{BIN}, $$

where the input binary vector is interpreted according to the Input sign property (SIGNED or UNSIGNED) and converted to a 32-bit signed INTEGER.

Pin Description

BIN Input Variable bit BIT VECTOR
Input binary vector, always std_logic_vector. Width: Configurable via Input bits property (2 to 32 bits) Interpretation: Configurable via Input sign property (UNSIGNED or SIGNED)
Default: Must be connected
INT Output 1 bit INT

Output INTEGER signal. Type: VHDL INTEGER (32-bit signed) Range: -2,147,483,648 to 2,147,483,647

Output is combinational (zero latency).

Properties

Property window

Input bits InputSize

Set the number of bits of the input

Number of bits in the binary input vector (2 to 32 bits). Smaller widths are zero-extended (UNSIGNED) or sign-extended (SIGNED) to 32 bits.

Default: 32

Range: 2 – 32

Input sign InputSign

Select the sign/unsign of the input

Interpretation of the input binary vector: UNSIGNED (0 to 2^N-1) or SIGNED (two’s complement, -2^(N-1) to 2^(N-1)-1).

Default: UNSIGNED

Options: UNSIGNED SIGNED

Functional description

The component performs a direct type conversion from std_logic_vector to VHDL’s INTEGER type. The VHDL INTEGER type is a 32-bit signed integer with range -2,147,483,648 to 2,147,483,647.

Conversion process

The conversion depends on the Input sign property:

For UNSIGNED input: $$ \mathrm{INT} = \sum_{i=0}^{N-1} \mathrm{BIN}[i] \times 2^i $$

For SIGNED input (two’s complement): $$ \mathrm{INT} = -\mathrm{BIN}[N-1] \times 2^{N-1} + \sum_{i=0}^{N-2} \mathrm{BIN}[i] \times 2^i $$

where:

  • $N$ → Input bits (2 to 32)
  • BIN → Input binary vector
  • INT → Output INTEGER value

Input interpretation modes

The Input sign property determines how the input binary is interpreted:

  • UNSIGNED: Input represents values 0 to $2^N - 1$

    • All bits contribute positively to the result
    • Example: 0xFF (8 bits) → 255

  • SIGNED: Input uses two’s complement representation

    • MSB is the sign bit
    • Range: $-2^{N-1}$ to $2^{N-1} - 1$
    • Example: 0xFF (8 bits) → -1

Range and overflow considerations

  • Input width $N$ can be 2 to 32 bits
  • For $N < 32$ bits:
    • UNSIGNED inputs are zero-extended to 32 bits
    • SIGNED inputs are sign-extended to 32 bits
  • For $N = 32$ bits:
    • UNSIGNED: values 0 to 4,294,967,295 are mapped
    • Values > 2,147,483,647 will appear negative (overflow)
    • SIGNED: full -2,147,483,648 to 2,147,483,647 range

Example conversions

For 16-bit UNSIGNED input:

  • BIN = 0x002A → INT = 42
  • BIN = 0xFFFF → INT = 65535
  • BIN = 0x0100 → INT = 256

For 8-bit SIGNED input:

  • BIN = 0x2A → INT = 42
  • BIN = 0xFF → INT = -1
  • BIN = 0x7F → INT = 127
  • BIN = 0x80 → INT = -128

For 32-bit UNSIGNED input (overflow case):

  • BIN = 0x80000000 → INT = -2,147,483,648 (overflow, appears negative)
  • BIN = 0xFFFFFFFF → INT = -1 (overflow, appears negative)

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Binary To Integer 0

Output is available immediately in the same clock cycle.

Typical use cases

  • Converting binary data to integers for arithmetic operations
  • Interfacing bit-level logic with integer arithmetic units
  • Reading configuration registers as integer values
  • Type conversion for component interfacing