TM
Block Preview

Introduction

This block performs a left shift operation on time-multiplexed (TM) data streams. Each bit of the input is shifted left by the specified Shift amount, and zeros are inserted in the vacant rightmost positions.

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT}(n) = \mathrm{IN}(n) \ll S, $$

where $S$ is the Shift parameter. The TM Factor property determines how many parallel samples are processed per clock cycle.

Pin Description

IN Input Variable bit TM
Input binary data, always TM. Width: Input Size × TM Factor Each TM phase receives its corresponding slice of the input bus.
Default: Must be connected
OUT Output 16 bit TM

Left-shifted output, always TM (same factor as IN). Width: Output Size × TM Factor

  • Output Size = Input Size (SAME SIZE mode)
  • Output Size = Input Size + Shift (SHIFTED SIZE mode)

Output is combinational (zero latency).

Properties

Property window

Input Size InputWordSize

Set the input word size in bits (per phase)

Number of bits per input sample ($N_\text{in}$). Range: 2 – 16384. Each TM phase processes samples of this width.

Default: 16

Range: 2 – 16384

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Time-multiplexing factor (number of parallel phases). Allowed values: 2, 4, 8, 16, 32 (up to 32). Higher values increase throughput proportionally but consume more FPGA resources (one shift instance per TM phase).

Default: 4

Range: 2 – 32

Shift Shift

Number of bit to be shifted

Number of bit positions to shift left ($S$). Range: 0 – 16384. When Shift = 0, output equals input (no operation). When Shift ≥ Input Size (in SAME SIZE mode), output is all zeros.

Default: 1

Range: 0 – 16384

Output Size OutputSize

Select if output should have same size of input or should be INPUT_SIZE-SHIFT

Output bit width mode:

  • SAME SIZE → Output width = Input width (MSBs truncated)
  • SHIFTED SIZE → Output width = Input width + Shift (no truncation)

Choose SHIFTED SIZE when all shifted bits must be preserved. Choose SAME SIZE for fixed-width operations with wrap-around.

Default: SAME SIZE

Options: SAME SIZE SHIFTED SIZE

Functional description

The component implements a bitwise left shift in VHDL, replicated N times (where N = TM Factor) to support time-multiplexed data streams.

For each TM phase, the operation is:

$$ y[i] = x[i] \ll S, $$

where:

  • $x[i]$ → input sample at phase $i$
  • $y[i]$ → output sample at phase $i$
  • $S$ → shift amount (constant across all phases)

The left shift operation appends $S$ zero bits to the right of the input:

$$ y = x \times 2^S $$

Output size modes

The block offers two output width configurations:

  • SAME SIZE: Output width = Input width The $S$ most significant bits are discarded (truncated).

  • SHIFTED SIZE: Output width = Input width + Shift amount No truncation; all shifted bits are preserved.

Example

Given an 8-bit input 10110011 and shift amount = 3:

  • Full result (11 bits): 10110011000
  • SAME SIZE (8 bits): 10011000 (MSBs discarded)
  • SHIFTED SIZE (11 bits): 10110011000 (all bits preserved)

Mathematical background

Left shift by $S$ positions is equivalent to multiplication by $2^S$:

$$ x \ll S = x \times 2^S $$

This is commonly used for:

  • Fast multiplication by powers of 2
  • Bit alignment and packing operations
  • Scaling in fixed-point arithmetic

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Left Shift TM 0

All TM phases are processed in parallel within the same clock cycle.

Typical use cases

  • Fast multiplication by powers of 2 in signal processing
  • Bit field manipulation and packing
  • Fixed-point rescaling (e.g., converting fractional widths)
  • Building blocks for barrel shifters and ALUs

Waveform example

Example with TM Factor = 4, Shift = 2, Input = [0x5, 0x7, 0xA, 0xF] (4-bit), SAME SIZE mode.

Note: Output is available immediately (combinational logic). Values shown in hex: 5 « 2 = 0x14 → 0x4 (truncated), 7 « 2 = 0x1C → 0xC, etc.