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Introduction

Not recommended for new designs. Use QDC/PSD HLS instead for improved functionality including baseline subtraction, configurable PSD formula, pre-trigger integration, and pile-up rejection counters.

The PSD Qlong/Qshort block implements a basic pulse shape discrimination algorithm using the charge integration method.

PSD can be used to distinguish different particle types (e.g., neutrons from gammas) based on their scintillation pulse shape differences.

Pin Description

In Input 16 bit BIT VECTOR
TRIGGER Input 1 bit BIT
Trigger input pulse. Starts the integration process. HIGH for one clock cycle at the pulse detection time.
Default: Must be connected
LONG Input 16 bit BIT VECTOR
16-bit long integration time in clock cycles. Duration of the Qlong integration window. Default: 256 (0x0100).
Default: 256
SHORT Input 16 bit BIT VECTOR
16-bit short integration time in clock cycles. Duration of the Qshort integration window. Must be less than LONG. Default: 256 (0x0100).
Default: 256
PILEUP Input 16 bit BIT VECTOR
CLK Input 1 bit BIT
System clock input. All operations are synchronous to the rising edge. Default: CLK_ACQ for DT5550 (80 MHz), CLK_50 for V2495 (50 MHz).
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous reset. Restarts the filtering process. Default: Global reset.
Default: Default Board Reset
PSD Output 32 bit BIT VECTOR
32-bit PSD ratio output. Fixed-point ratio of Qshort/Qlong. Maximum value (2^32) when Qshort = Qlong. Value is 0 when Qshort = 0.
Qlong Output 32 bit BIT VECTOR
Qshort Output 32 bit BIT VECTOR
DV Output 1 bit BIT
Data valid strobe. HIGH for one clock cycle when PSD, QLong, and QShort outputs are valid.
AN In 16 bit
16-bit analog input signal from ADC. Connected to the detector output.
Default: Must be connected
PILEUP INIB 16 bit
16-bit pile-up rejection inhibit time in clock cycles. Must be at least equal to LONG. Events occurring during this window are rejected. Default: 256 (0x0100).
Default: 256
QLong 32 bit
32-bit long integration result. Total charge integrated over the LONG time window.
QShort 32 bit
32-bit short integration result. Total charge integrated over the SHORT time window.

Usage

PSD Algorithm

The block calculates the PSD value using the following formula:

$$ \text{PSD} = \frac{Q_{\text{short}}}{Q_{\text{long}}} \times 2^{32} $$

where:

  • Qlong: Charge integrated over the long time window
  • Qshort: Charge integrated over the short time window

The PSD output is a 32-bit fixed-point value. Maximum value (2^32) occurs when Qshort = Qlong.

Limitations

This legacy block has several limitations compared to the newer QDC/PSD HLS block:

Feature PSD Legacy QDC/PSD HLS
Pre-trigger integration No Yes
Baseline subtraction No Yes
PSD formula selection Fixed (Qshort/Qlong) Selectable
Pile-up rejection counters No Yes
16-bit scaled outputs No Yes
Timestamp capture No Yes
Gate outputs No Yes

Pre-Trigger Integration Workaround

This block does not implement pre-trigger integration. If pre-trigger capture is required, an external delay must be added to align the trigger with the signal.

Pile-Up Rejection

The block implements basic pile-up rejection by inhibiting measurements if two triggers occur too close together (within the LONG integration window).

Migration to QDC/PSD HLS

For new designs, use the QDC/PSD HLS block which provides:

  • Pre-trigger integration (PRE_INT parameter)
  • Real-time baseline subtraction
  • Selectable PSD formula (Qlong/Qshort or Qshort/Qlong)
  • Pile-up rejection with counters (REJ_CNT, DREJ_CNT)
  • Both 32-bit and 16-bit charge outputs
  • Timestamp capture
  • Integration gate outputs for monitoring