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Introduction

The Gate Differentiator computes the difference between two consecutive integration windows, producing a derivative-like output:

$$ \mathrm{OUT}[n] = \sum_{i=0}^{W-1} \mathrm{IN}[n+i] - \sum_{i=0}^{W-1} \mathrm{IN}[n-W+i] $$

where W is the window length. This operation is fundamental in Constant Fraction Discriminators (CFD) and timing trigger circuits for particle detection systems.

The block provides handshake signals (DV_OUT, READY) for integration with trigger and data acquisition systems.

Pin Description

DATA_IN Input 32 bit BIT VECTOR
Input pulse signal to be differentiated. Width: 32 bits (signed fixed-point). Typically detector output or shaped pulse.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable input, active high. Controls differentiator operation. Default: tied to ‘1’ (free-running).
Default: 1
WINDOW Input 16 bit BIT VECTOR
Differentiator window length in clock cycles. Width: 16 bits (unsigned integer). Determines integration time for both windows. Larger values smooth noise but reduce timing precision. Default: 16 (x"0010").
CLEAR Input 1 bit BIT
Asynchronous clear signal, active high. Immediately resets internal buffers and state. Default: tied to ‘0’ (inactive).
CLK Input 1 bit BIT
System clock. Drives internal delay line and computation.
Default: Default Board Clock
OUT Output 32 bit BIT VECTOR
Differentiated output signal. Width: 32 bits (signed fixed-point). Zero-crossing indicates pulse peak timing. Valid when DV_OUT is high.
DV_OUT Output 1 bit BIT
Data Valid output signal, active high. Indicates valid differentiated output on OUT.
READY Output 1 bit BIT
Ready signal, active high. Indicates differentiator is idle and ready for new data.

Functional description

The differentiator implements a windowed difference operation:

$$ y[n] = \int_{t=n}^{n+W} x[t] , dt - \int_{t=n-W}^{n} x[t] , dt $$

This produces:

  • Positive output: When signal is rising
  • Zero crossing: At pulse peak (timing reference)
  • Negative output: When signal is falling

Applications in timing

In CFD circuits, the zero-crossing of the differentiator output provides a timing mark independent of pulse amplitude. The WINDOW parameter controls the derivative time constant:

  • Shorter windows: Faster response, more noise sensitivity
  • Longer windows: Smoother output, reduced timing jitter

Window length

The WINDOW input sets the integration length for both windows:

  • Width: 16 bits (unsigned)
  • Default: 16 samples (x"0010")
  • Typical range: 4 – 256 samples

Control signals

  • CE: Clock enable for operation
  • CLEAR: Immediate reset of internal state
  • READY: Indicates idle state, ready for new data

Latency

Fixed latency of 2 clock cycles.

Typical use cases

  • Zero-crossing detection in CFD circuits
  • Timing extraction in nuclear spectroscopy
  • Pulse shape discrimination
  • Leading-edge timing triggers