TM
Block Preview

Introduction

The Multi MUX TM block is the time-multiplexed version of the Multi MUX: refer to that block’s help for the full signal-set model (forward IN->OUT signals, reverse OUT<-IN signals, per-signal Registered option, per-signal unselected value).

The only difference is the pin type: every data signal is a TM bus carrying TM factor samples per clock cycle, so a signal configured as W bits wide becomes a W x TM bit physical port. SEL is a plain vector and selects the whole channel: the routing is bus-level and identical for every sample of the TM word (there is no per-sample selection).

The TM factor (2/4/8/16/32) is chosen inside the same Multi MUX Designer window, which shows the TM row for this variant.

Pin Description

WORD_0 Input 32 bit TM
DV_0 Input 1 bit TM
WORD_1 Input 32 bit TM
DV_1 Input 1 bit TM
WORD_2 Input 32 bit TM
DV_2 Input 1 bit TM
WORD_3 Input 32 bit TM
DV_3 Input 1 bit TM
BUSY Input 1 bit TM
SEL Input 1-6 bit BIT VECTOR
Channel selector, ceil(log2(N)) bits, plain vector.
Default: Must be connected
WORD Output 32 bit TM
DV Output 1 bit TM
BUSY_0 Output 1 bit TM
BUSY_1 Output 1 bit TM
BUSY_2 Output 1 bit TM
BUSY_3 Output 1 bit TM
NAME_k / NAME 1-4096 x TM bit
Same pin scheme as the Multi MUX, but every data pin is a TM bus of Width x TM bits (drawn as a TM pin of Width bits in the diagram).
CLK 1 bit
Clock input; present only when at least one signal is registered. Default: Acquisition clock.

Properties

Mux configuration (use editor) MuxConfig

Signal set of the Multi MUX TM, produced by the Multi MUX Designer

Hidden property holding the whole signal-set configuration (including the TM factor); edit it exclusively through the Multi MUX Designer.

Default: 4;4|WORD,32,F,0,0|DV,1,F,0,0|BUSY,1,R,0,1

Usage

Notes

  • All the routing rules of the plain Multi MUX apply unchanged.
  • The register option re-times the full TM bus at once - the latency is one clock of the fast (system) clock domain the bus lives in.
  • SEL and CLK are plain 1x signals, never time-multiplexed.

Resources & Timing

  • Latency: 0 clocks (combinational signals) or 1 clock (registered signals)

  • Throughput: combinational routing, no stall

Pure LUT routing plus one register layer per registered signal. Resource usage scales with the total signal width times N times TM.