Xilinx
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Introduction

The block computes the absolute value of floating-point inputs, effectively clearing the sign bit of IEEE-754 encoded values. On every clock cycle with CE = 1, the operation performs

$$ \mathrm{F}(n) = |\mathrm{A}(n)|, $$

where both input A and output F follow IEEE-754 single or double precision format.

The operation is implemented with the Xilinx floating_point IP core configured for Absolute operation with zero latency (purely combinatorial).

Pin Description

A Input Variable bit BIT VECTOR
Floating-point input value (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Can be any valid floating-point number including negative, zero, infinity, or NaN.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable (tvalid), active high. When CE = 1, input A is processed and output F is valid. Can be tied to ‘1’ for continuous operation.
Default: 1
READY_IN Input 1 bit BIT
Downstream ready signal (tready input), active high. Indicates if downstream logic can accept new data. Can be tied to ‘1’ if backpressure is not needed.
F Output 32 bit BIT VECTOR
Floating-point output value (IEEE-754), absolute value of input. Width: 32 bits (Single) or 64 bits (Double). Valid when DV = 1 (same cycle as CE = 1).
DV Output 1 bit BIT
Data Valid output (tvalid), active high. Mirrors CE for zero-latency operation. Indicates when output F contains valid data.
READY_OUT Output 1 bit BIT
Upstream ready signal (tready output), active high. Indicates this block can accept new input data. Always ready for zero-latency combinatorial operation.

Properties

Property window

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Floating-point precision for both input and output:

  • Single → 32-bit (8-bit exponent, 24-bit mantissa including implicit bit)
  • Double → 64-bit (11-bit exponent, 53-bit mantissa including implicit bit)

The operation preserves the precision format end-to-end.

Default: Single

Options: Single Double

Functional description

The component computes the absolute value:

$$ F = |A| = \begin{cases} A & \text{if } A \geq 0 \ -A & \text{if } A < 0 \end{cases} $$

In hardware, this is efficiently implemented by clearing the sign bit (MSB) of the IEEE-754 representation.

Special cases

The absolute value operation handles IEEE-754 special values:

  • |+0| = +0
  • |-0| = +0
  • |+Inf| = +Inf
  • |-Inf| = +Inf
  • |NaN| = NaN (sign bit cleared, preserving payload)

Timing

Zero-latency operation:

Clock cycle Event
0 Input A presented with CE = 1
0 Output F valid immediately (same cycle)

Since the operation is combinatorial, DV follows CE without delay.

Typical use cases

  • Magnitude computation in complex signal processing
  • Distance metrics (L1 norm components)
  • Envelope detection in RF/audio processing
  • Error magnitude computation in control systems