TM - FIXED TO FLOAT CONVERTER
Time-multiplexed fixed-point to floating-point converter. Converts multiple channels of fixed-point data to IEEE-754 format (single or double precision) with configurable input formats, scalar broadcast support, and 1-8 stage pipeline. Enables seamless integration between fixed and floating-point domains.
Introduction
The block performs time-multiplexed fixed-point to floating-point conversion across
multiple data streams. On every rising edge of CLK, when IN_DV = 1, the converter
computes
$$ \mathrm{OUT}_i(n) = \text{float}(\mathrm{IN}_i(n)), \quad i = 0, \ldots, \text{TM}-1, $$
where each subscript $i$ represents a different TM phase, TM is the time-multiplexing factor (4, 8, 16, or 32), and the output follows IEEE-754 single (32-bit) or double (64-bit) precision format.
The input can be either time-multiplexed (converting multiple channels in parallel) or scalar (broadcasting a single fixed-point value to all TM output phases).
This component enables efficient multi-channel conversion for applications requiring the dynamic range and precision of floating-point representation.
Pin Description
Fixed-point input, can be time-multiplexed or scalar. If Input is TM = YES: Width: (Integer Bits + Fractional Bits) × TM Factor Contains TM phases: [IN0, IN1, …, IN(TM-1)] If Input is TM = NO: Width: Integer Bits + Fractional Bits Single value broadcast to all output phases
Interpreted as signed fixed-point with configurable format.
Time-multiplexed floating-point output (always TM). Width: (32 bits for Single or 64 bits for Double) × TM Factor. Contains IEEE-754 results: [OUT0, OUT1, …, OUT(TM-1)]. Valid when OUT_DV = 1.
Format: IEEE-754 single or double precision.
Properties
Number of fractional bits in the fixed-point input. Range: 0-64. Default: 0. Determines fractional precision.
Example formats:
- Q16.0 (16 int, 0 frac) → integers -32768 to 32767
- Q8.8 (8 int, 8 frac) → values -128.0 to 127.996
- Q1.15 (1 int, 15 frac) → values -1.0 to 0.99997
Determines if input is time-multiplexed:
- NO → Input is scalar, broadcast to all TM phases
- YES → Input is TM, phase-by-phase conversion Default: YES
Output floating-point precision format:
- SINGLE (IEEE 754 32-bit) → 32 bits per value (8-bit exp, 24-bit mantissa)
- DOUBLE (IEEE 754 64-bit) → 64 bits per value (11-bit exp, 53-bit mantissa) Default: SINGLE
Choose Double for:
- Wide dynamic range requirements (>10³⁸)
- High precision (>7 decimal digits)
- Scientific computing
Choose Single for:
- Resource efficiency
- Typical DSP applications
- When 7 digits precision suffices
Functional description
The component implements time-multiplexed fixed-to-float conversion:
$$ \text{OUT}[i] = \text{float}\left(\frac{\text{IN}[i]}{2^{F_{\text{bits}}}}\right), $$
where:
IN[i]→ fixed-point input, phase $i$ (TM or scalar)OUT[i]→ floating-point output (IEEE-754), phase $i$ (always TM)- $F_{\text{bits}}$ → number of fractional bits in input format
The input format is configurable:
- Integer bits (1-64)
- Fractional bits (0-64)
- Total width = Integer bits + Fractional bits
IEEE-754 Floating-Point Format
The output follows standard IEEE-754 encoding:
Single precision (32-bit):
- 1 sign bit
- 8 exponent bits (bias = 127)
- 23 mantissa bits (24 with implicit leading 1)
- Range: ±1.18×10⁻³⁸ to ±3.40×10³⁸
- Precision: ~7 decimal digits
Double precision (64-bit):
- 1 sign bit
- 11 exponent bits (bias = 1023)
- 52 mantissa bits (53 with implicit leading 1)
- Range: ±2.23×10⁻³⁰⁸ to ±1.80×10³⁰⁸
- Precision: ~16 decimal digits
Conversion Process
The fixed-to-float conversion involves:
- Normalization: Find the position of the most significant ‘1’ bit
- Exponent calculation: Compute IEEE-754 biased exponent
- Mantissa extraction: Extract and align mantissa bits
- Rounding: Round to nearest even (banker’s rounding)
- Special cases: Handle zero, denormals (optional)
Time Multiplexing
Time multiplexing processes multiple independent conversions through shared hardware:
| Clock cycle | Processing phase |
|---|---|
| 0 | Phase 0 → OUT[0] = float(IN[0]) |
| 1 | Phase 1 → OUT[1] = float(IN[1]) |
| … | … |
| TM-1 | Phase TM-1 → OUT[TM-1] = float(IN[TM-1]) |
| TM | Phase 0 (next cycle) |
Scalar Broadcast Mode
When Input is TM = NO, a single fixed-point value is broadcast to all output phases:
OUT[0] = float(IN)
OUT[1] = float(IN)
...
OUT[TM-1] = float(IN)
This is useful for:
- Broadcasting constants to all channels
- Converting a single control value for parallel processing
- Test pattern generation
Pipeline and Timing
The Pipeline Length property (1-8 stages) controls latency versus maximum clock frequency:
| Pipeline Length | Latency (clock cycles) | Typical Fmax |
|---|---|---|
| 1 | TM × 1 | 300-350 MHz |
| 2 | TM × 2 | 400-450 MHz |
| 3 | TM × 3 | 500-550 MHz |
| 4-8 | TM × 4-8 | 550-600 MHz |
Total latency = Pipeline Length × TM factor
Precision Considerations
Loss of precision can occur when:
- Fixed-point has more precision bits than float mantissa
- Single (23 mantissa bits) ← Q16.16 (32 total bits): 9 bits lost
- Double (52 mantissa bits) ← Q32.32 (64 total bits): 12 bits lost
No loss when:
- Total fixed-point bits ≤ mantissa bits + 1
- Example: Q16.0 → Single precision (perfect conversion)
Typical use cases
- Converting ADC samples to floating-point for DSP algorithms
- Interface between fixed-point front-ends and floating-point processing
- Multi-channel sensor data normalization
- Preparing data for floating-point FFT/filter banks
- Machine learning inference preprocessing
- Mixed-precision computing pipelines
Waveform example
Example with TM=4, Pipeline=3, scalar input: