Xilinx
TM
Block Preview

Introduction

This block implements a fine-grained programmable TM delay where the DELAY input specifies delays in individual samples, not TM groups. This allows sub-group timing precision for advanced applications.

Note: Max Delay Value is specified in samples (not TM groups), allowing fractional-group delays.

Pin Description

IN Input Variable bit TM
Time-multiplexed input. Width: Bit Width × TM Factor.
Default: Must be connected
DELAY Input 16 bit BIT VECTOR
Delay amount in samples (not groups). Range: 0 to Max-1. 16-bit std_logic_vector.
Default: Must be connected
CLK Input 1 bit BIT
Clock signal (HLS ap_clk).
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset (HLS ap_rst).
Default: Must be connected
OUT Output Variable bit TM
Time-multiplexed delayed output. Width: Bit Width × TM Factor.
DV Output 1 bit BIT
Data Valid output signal. Indicates when OUT contains valid delayed data. 1-bit std_logic.

Properties

Property window

Max Delay Value MaxDelayValue

Set the amount of memory to reserve for this delay line (in samples, not TM groups)

Maximum delay in samples (not groups). Range: 256-131072. Memory allocated = ceiling(MaxDelayValue / TMFactor) + 1 TM groups.

Default: 4096

Options: 256 512 1024 2048 4096 8192 16384 32768 65536 131072

Bit Width BusWidth

Set the size in bits of the signal to be delayed

Bit width per TM phase. Range: 1-1024.

Default: 1

Range: 1 – 1024

TM Factor TimeMultiplexing

Time Multiplexing factor

TM Factor. Allowed: 4, 8, 16, 32.

Default: 4

Options: 4 8 16 32

Functional description

Unlike the standard Variable Delay TM which delays entire TM groups, this variant:

  • Delays at sample resolution (DELAY counts individual samples, not groups)
  • Requires Xilinx FPGA (uses Vivado HLS)
  • Generates custom IP core at compile time
  • Provides DV (data valid) output signal

Implementation

Uses Vivado HLS to generate optimized delay logic. The component is synthesized from C++ source code (see Resources/CODE_delay_fine_tm) during project compilation.

Max Delay in samples

If TM Factor = 4 and Max Delay = 4096:

  • You can delay by 4096 samples total
  • This equals 1024 TM groups (4096 / 4)
  • Fine control: DELAY can be any value 0-4095

Timing

Latency = 1 clock cycle (inherent to HLS pipeline).

Typical use cases

  • High-precision timing applications
  • Fractional-group delay requirements
  • Applications needing data-valid signaling

Design considerations

Xilinx-only: Requires Vivado HLS toolchain. Not supported on Intel FPGAs.