TM
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Introduction

This block generates constant fixed-point values for time-multiplexed (TM) data streams. It produces fixed-point constants across multiple TM phases, with each phase receiving its own configurable floating-point value automatically converted to fixed-point representation.

The component supports two operating modes:

  • Same value for all phases: One constant replicated across all TM phases
  • Different values per phase: Unique constant for each TM phase

Fixed-point format uses Q-notation: Q(FixedBits-1).DecimalBits, where:

  • FixedBits: Integer part width (including sign bit)
  • DecimalBits: Fractional part width

The output is purely combinational with zero clock latency, suitable for direct use in TM fixed-point arithmetic pipelines.

Pin Description

CONST Output Variable ((FixedBits+DecimalBits) × TMFactor) bit TM

Constant fixed-point output, always TM (time-multiplexed). Width: (FixedBits + DecimalBits) × TM Factor bits.

Each TM phase occupies a contiguous slice representing a signed fixed-point number in Q-format. The output is combinational (zero latency) and available immediately after FPGA configuration.

TM phase ordering: Phase 0 occupies LSBs, Phase N-1 occupies MSBs.

Properties

Property window

Name Name

Set the name of the constant.

Optional custom label for the component. If specified, replaces the default title “Const Fixed Point TM” on the schematic symbol. Leave blank to use default.
Fixed bits FixedBits

Set the number of bits for the integer part of the number (including sign)

Number of bits for the integer part (including sign bit) per phase. Minimum: 1. Determines the representable range for each phase: [-2^(FixedBits-1), 2^(FixedBits-1) - 2^(-DecimalBits)].

Default: 2

Decimal bits DecimalBits

Set the number of bits for the decimal part of the number

Number of bits for the fractional part per phase. Determines precision/resolution: 2^(-DecimalBits). Higher values provide better accuracy but require more bits. Typical range: 8 to 32.

Default: 30

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Time-multiplexing factor (number of parallel phases). Allowed values: 1 to 32. Determines how many constant values are generated per clock cycle. Must match downstream TM components.

Default: 4

Range: 1 – 32

Same value for all phases SameForAllPhases

If true, the same constant value is used for all TM phases. If false, specify different values for each phase separated by comma, semicolon or space

If True, use a single Value for all TM phases (replicated). If False, provide exactly TMFactor comma/semicolon/space-separated floating-point values (one per phase). Mismatch causes compilation error.

Default: True

Value Value

Set the value(s) of the constant. If ‘Same for all phases’ is true: Use single floating point value (e.g., 3.14159) If ‘Same for all phases’ is false: Use comma/semicolon/space separated values (e.g., 1.5,2.3,3.7,4.2)

Floating-point constant value(s). If SameForAllPhases=True: single value (e.g., 3.14159). If SameForAllPhases=False: TMFactor values separated by comma, semicolon, or space (e.g., 1.5,2.3,3.7,4.2 for TM=4). Use comma or period as decimal separator. Values are automatically converted to fixed-point format.

Default: 0

Functional description

The component implements a time-multiplexed constant fixed-point source in VHDL. For TM Factor = $N$, the output contains $N$ fixed-point values:

$$ \mathrm{OUT}(t) = [V_0, V_1, V_2, \ldots, V_{N-1}] $$

where each $V_i$ is converted from floating-point to fixed-point:

$$ V_i = \lfloor \text{FloatValue}_i \times 2^D \rceil $$

with $D$ = DecimalBits and each value having total width $F + D$ bits ($F$ = FixedBits).

TM Factor and phase assignment

The TM Factor determines the number of parallel constant phases:

TM Factor Phases per Clock Total Output Width
2 2 (FixedBits+DecimalBits) × 2
4 4 (FixedBits+DecimalBits) × 4
8 8 (FixedBits+DecimalBits) × 8
16 16 (FixedBits+DecimalBits) × 16
32 32 (FixedBits+DecimalBits) × 32

Each phase occupies a contiguous slice of the output bus.

Operating modes

Mode 1: Same value for all phases

When SameForAllPhases = True, a single floating-point value is replicated:

  Value: 3.14159
TM Factor: 4
FixedBits: 4, DecimalBits: 12
Total: 16 bits per phase

Output (64 bits): [3.14159, 3.14159, 3.14159, 3.14159] (all in Q3.12)
                   Phase0   Phase1   Phase2   Phase3

Mode 2: Different values per phase

When SameForAllPhases = False, provide comma/semicolon/space-separated values:

  Value: 1.0, 2.5, -1.5, 0.707
TM Factor: 4
FixedBits: 4, DecimalBits: 12

Output (64 bits): [1.0, 2.5, -1.5, 0.707] (all in Q3.12)
                   Phase0 Phase1 Phase2 Phase3

Important: The number of values must exactly match the TM Factor, or a compilation error will occur.

Fixed-point conversion

Each floating-point value is converted to fixed-point using the formula:

$$ \text{Fixed} = \text{round}(V_{\text{float}} \times 2^{\text{DecimalBits}}) $$

The result is a signed integer with total width = FixedBits + DecimalBits.

Q-format notation

The output uses Q-format: Q(F-1).D, where:

  • $F-1$ = number of integer bits (excluding sign)
  • $D$ = number of fractional bits

For example, Q1.30 has:

  • 1 sign bit + 1 integer bit = 2 FixedBits
  • 30 DecimalBits
  • Total: 32 bits per phase
  • Range: $[-2, 2 - 2^{-30}]$
  • Resolution: $2^{-30}$

Range and precision

Range (per phase): $$ \left[-2^{F-1}, 2^{F-1} - 2^{-D}\right] $$

Resolution (per phase): $$ 2^{-D} $$

Values outside the range will overflow and be truncated during compilation.

Implementation details

The VHDL implementation concatenates all phase values into a single bus:

vhdl 
  signal CONST : STD_LOGIC_VECTOR(TotalWidth-1 downto 0);
CONST <= VV(N-1) & VV(N-2) & ... & VV(1) & VV(0);

where each VV(i) is:

vhdl 
  VV(i) = conv_std_logic_vector(round(Value(i) * 2^DecimalBits), TotalBits)

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Constant Fixed-Point [TM] 0

All TM phases are available immediately (no pipeline delay).

Typical use cases

  • TM filter coefficients: Provide constant FIR/IIR coefficients for parallel TM filters
  • TM gain stages: Supply fixed-point scaling factors for multiple data streams
  • TM mathematical constants: Define π, e, or other constants for each TM phase
  • TM calibration values: Store per-channel calibration factors in fixed-point
  • TM control parameters: PID gains (Kp, Ki, Kd) for multi-channel controllers
  • TM lookup tables: Precomputed function values (sine, log, exp) for each phase

Example configurations

Example 1: Same value, all phases (TM=4, Q1.30) 

  Name: "PI"
Value: 3.14159265
FixedBits: 2
DecimalBits: 30
TMFactor: 4
SameForAllPhases: True

Output (128 bits):
Phase 0: 3.14159265 in Q1.30
Phase 1: 3.14159265 in Q1.30
Phase 2: 3.14159265 in Q1.30
Phase 3: 3.14159265 in Q1.30

Example 2: Different values per phase (TM=4, Q3.12) 

  Value: 1.0, 2.5, -1.5, 0.707
FixedBits: 4
DecimalBits: 12
TMFactor: 4
SameForAllPhases: False

Output (64 bits):
Phase 0: 1.0    → 0x1000
Phase 1: 2.5    → 0x2800
Phase 2: -1.5   → 0xE800 (negative)
Phase 3: 0.707  → 0x0B50

Example 3: Filter coefficients (TM=8, Q0.15) 

  Value: 0.5, 0.25, 0.125, 0.0625, 0.03125, 0.015625, 0.0078125, 0.00390625
FixedBits: 1
DecimalBits: 15
TMFactor: 8
SameForAllPhases: False

Use case: 8-tap FIR filter with exponentially decaying coefficients

Example 4: Gain factors (TM=2, Q7.24) 

  Value: 12.5, -6.25
FixedBits: 8
DecimalBits: 24
TMFactor: 2
SameForAllPhases: False

Use case: Dual-channel amplifier with positive and negative gains