RF Real AGC (linear)

Introduction link

The Real AGC (linear) block multiplies the input by an adaptive gain and drives a control loop that pushes the output power toward a fixed target. The full per-sample loop is:

      y   = clamp( (x * gain) >> GAIN_FRAC , OUT_MIN , OUT_MAX )
    avg += (y*y - avg) >> AVG_SHIFT          (leaky power estimate)
    err  = TARGET - avg
    gain += err >> LOOP_SHIFT                 (integrator / loop filter)
    gain = clamp(gain, MIN_GAIN, MAX_GAIN)
  

It is a linear AGC: the gain is applied as a plain multiply and the error is driven from the mean-square (y*y) power estimate rather than a log/dB detector. gain is an unsigned fixed-point number with GainFrac fractional bits, so gain = 2^GainFrac corresponds to unity gain.

      IN ──▶(×)──▶[ clamp ]──▶ OUT
           ▲                  │
          gain ◀─[ loop ]◀─[ y*y avg ]◀─┘
  

When the output power sits below the target, err is positive and the integrator ramps the gain up; when it exceeds the target the gain ramps down. The steady state is reached when avg ≈ TARGET.

Pin Description link

Properties link

Usage link

Control-loop model link

Three state elements form the loop:

1. avg — a leaky-integrator (first-order IIR) estimate of the output power E[y^2], updated as avg += (y*y - avg) >> AvgShift. This is a one-pole low-pass with time constant ~2^AvgShift samples; it smooths the instantaneous y*y so the loop reacts to envelope power rather than sample-by-sample ripple.
2. err = TARGET - avg — the power error, where TARGET = 2^TargetLog2.
3. gain — an integrator updated by gain += err >> LoopShift. A larger LoopShift makes each correction smaller, i.e. a slower, smoother AGC; a smaller value tracks faster but with more gain ripple / possible pumping.

Because the error feeds an integrator, the loop has zero steady-state power error (within quantisation): at lock avg ≈ 2^TargetLog2.

Target power note (real vs complex) link

For a pure sinusoid of amplitude A, the real signal has mean(y^2) = A^2 / 2, whereas a complex tone A*(cos + j*sin) has |.|^2 = A^2 at every sample. The two AGCs therefore lock a sinusoid to different amplitudes for the same TargetLog2. To get the same output level from this real AGC as from the complex AGC, set TargetLog2 one bit lower here.

Fixed-point datapath and bit widths link

All signal data is signed two’s complement; the gain is unsigned.

• IN : signed InputSize bits.
• OUT : signed OutputSize bits, clamped (saturated) to [-2^(OutputSize-1), 2^(OutputSize-1) - 1]. Typical OutputSize = InputSize + 2 to give the AGC headroom to boost small inputs without immediate clipping.
• gain : unsigned GainSize bits, GainFrac fractional bits. Unity = 2^GainFrac.
• Product x * gain : InputSize + GainSize bits, arithmetic-shifted right by GainFrac to align back to sample scale.
• Power estimate avg and y*y : signed 2*OutputSize + 8 bits — wide enough to hold the squared full-scale output plus 8 guard bits for the leaky-integrator accumulation.
• Gain update is computed in GainSize + 4 bits to avoid overflow during the clamp.

Gain limits (clamp) link

The gain integrator is bounded to keep the loop stable and prevent runaway on silence:

      MIN_GAIN = 2^(GainFrac - 4)          ->  linear min = 1/16  (-24 dB)
    MAX_GAIN = 2^GainSize - 1            ->  linear max ≈ 2^(GainSize - GainFrac)
  

With the defaults (GainSize = 18, GainFrac = 12) the gain ranges from 1/16 up to ≈ 2^6 = 64 (about +36 dB). Widen GainSize to allow more boost of very weak signals.

Feedback / state registers and reset link

RESET is the HLS synchronous reset (ap_rst). On reset the loop state is initialised to a safe starting point:

• gain = 2^GainFrac (unity gain), so the very first output equals the input (scaled to OUT) before the loop adapts.
• avg = 0, so the loop initially sees maximum positive error and begins ramping the gain toward the target at the rate set by LoopShift.

After release the AGC converges to the target power over roughly 2^LoopShift (loop) combined with 2^AvgShift (envelope smoothing) samples; the dominant term is normally LoopShift.

Latency and throughput link

• #pragma HLS PIPELINE II=1 : one sample per clock.
• 1-clock latency (registered output).
• All data ports use the ap_none interface — no ready/valid handshake. Every tuning value (TargetLog2, LoopShift, AvgShift, gain format) is baked in at synthesis time; no top-level control pins are created.

Tuning guidance link

• TargetLog2 — sets the output level: mean(y^2) = 2^TargetLog2, i.e. RMS ≈ 2^(TargetLog2/2). Keep RMS comfortably below 2^(OutputSize-1) to leave crest-factor headroom before the output clamp engages.
• LoopShift (12–20 typical) — attack/decay speed. Larger = slower and smoother, less pumping; smaller = faster tracking of level changes.
• AvgShift (4–10 typical) — envelope smoothing. Larger averages the power over more samples (steadier gain, slower response to bursts).

Typical applications link

• Constant-level audio / IF ahead of an FM/AM demodulator or a fixed-threshold detector.
• Fading compensation on a real IF channel (slow LoopShift).
• Normalising a variable-amplitude stream so a downstream fixed-point stage sees a predictable dynamic range.
• Squelch-friendly leveling — the MIN_GAIN floor stops the loop from amplifying noise to full scale during silence.

Resources & Timing link

• Latency: 1 clock cycle

• Throughput: 1 sample per clock (II=1)

Implemented with Vitis HLS. Single-multiplier signal path (x * gain) plus one squarer (y*y) for the power estimate — roughly two DSP48 slices, half the arithmetic of the complex AGC. Three state registers: gain, avg, and the pipelined output. No BRAM. On ap_rst, gain resets to unity (2^GainFrac) and avg to 0. The output clamp (saturation) and the gain-integrator clamp (MIN_GAIN..MAX_GAIN) keep the loop bounded and stable.