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Introduction

This block performs an arithmetic right shift operation on standard (non-TM) data streams. The vacant leftmost positions are filled with copies of the sign bit (MSB), making it suitable for signed two’s complement arithmetic.

Pin Description

IN Input Variable bit BIT VECTOR
Input binary data (two’s complement signed), non-TM.
Default: Must be connected
OUT Output Variable bit BIT VECTOR
Arithmetic right-shifted output (signed), non-TM, combinational.

Properties

Property window

Input Size InputWordSize

Set the input word size in bits

Default: 16

Range: 2 – 16384

Shift Shift

Number of bit to be shifted

Number of bit positions to shift right. Range: 0 – 127.

Default: 1

Range: 0 – 16384

Output Size OutputSize

Select if output should have same size of input or should be INPUT_SIZE-SHIFT

  • SAME SIZE → Output width = Input width
  • SHIFTED SIZE → Output width = Input width - Shift

Default: SAME SIZE

Options: SAME SIZE SHIFTED SIZE

InputWidth InputWidth
Number of bits per input sample. Range: 2 – 128. MSB is sign bit.

Functional description

The arithmetic right shift operation shifts bits right and replicates the MSB (sign bit):

$$ y = \text{sign_extend}(\lfloor x / 2^S \rfloor) $$

Output size modes

  • SAME SIZE: Output width = Input width
  • SHIFTED SIZE: Output width = Input width - Shift

Timing

Purely combinational with zero latency.