Block Preview

Introduction

This block performs a programmable right shift operation on standard (non-TM) data streams. The shift amount is dynamically controlled via the integer SHIFT input port.

Supports both:

  • Logical shift (Preserve Sign = false): Zero-fill
  • Arithmetic shift (Preserve Sign = true): Sign-extend

Pin Description

IN Input Variable bit BIT VECTOR
Input binary data (non-TM).
Default: Must be connected
SHIFT Input 1 bit INT
Shift amount control (integer, range 0 to Max Shift).
Default: Must be connected
CLK Input 1 bit BIT
Clock input (only when Latch Output = true).
Default: Default Board Clock
RESET Input 1 bit BIT
Reset input (only when Latch Output = true).
Default: Default Board Reset
OUT Output Variable bit BIT VECTOR
Right-shifted output (non-TM). Latency: 0 or 1 cycle.

Properties

Property window

Input Size InputWordSize

Set the input word size in bits

Default: 32

Range: 2 – 16384

Max Shift Shift

Number of maximum bit to be shifted

Default: 16

Range: 1 – 64

Preserve Sign Size PreserveSign

Select if keep sign bit in the output

  • false: Logical shift (zero-fill)
  • true: Arithmetic shift (sign-extend)

Default: False

Register Output LatchOutput

Select if latch the output. This will improve the performance but insert one clock cycle delay

  • false: Combinational output (0 latency)
  • true: Registered output (1 latency)

Default: True

InputWidth InputWidth
Number of bits per input sample. Range: 1 – 128.
MaxShift MaxShift
Maximum allowed shift amount. Range: 1 – 16.

Functional description

Implements a programmable barrel shifter (right shift) in VHDL.

Shift modes

  • Preserve Sign = false: Logical shift (zero-fill MSBs)
  • Preserve Sign = true: Arithmetic shift (sign-extend MSBs)

Latency modes

  • Latch Output = false: Combinational, latency = 0
  • Latch Output = true: Registered, latency = 1 clock cycle

Timing

Latency depends on Latch Output property: 0 or 1 clock cycles.