Xilinx
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Introduction

The IIR Butterworth - I Order block implements a first-order IIR (Infinite Impulse Response) filter operating in real time on FPGA. The component includes automatic filter coefficient calculation based on filter type (low/high pass) and cutoff frequency.

The Butterworth filter is widely used due to its maximally flat frequency response in the passband, meaning it does not have any ripples like Chebyshev or Elliptic filters.

Pin Description

IN Input 16U/17S bit BIT VECTOR
Fixed-point number input. Supports 16-bit unsigned or 17-bit signed input based on the DataTypeIn property.
Default: Must be connected
CLK Input 1 bit BIT
Input signal used as clock. All filter operations are synchronous to this clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous reset signal. Clears the filter state and all internal accumulators.
Default: Default Board Reset
OUT Output 16U/17S bit BIT VECTOR
Fixed-point number output. Same format as input (16-bit unsigned or 17-bit signed).

Properties

Property window

Type of filter Type

Select between low pass and high pass filter

Filter type selection. Available values: Low Pass, High Pass, default Low Pass.

Default: Low Pass

Options: Low Pass High Pass

Cutoff (KHz) Cutoff

Set the filter pole/zero position according to the selected bandwidth in KHz

Cutoff frequency in kHz. Must be less than half the sampling frequency (Nyquist limit).

Default: 1000

Input data type DataTypeIn

Select input data type

Input data format selection. Available values: Unsigned 16 bit, Signed 17 bit, default Unsigned 16 bit.

Default: UINT16

Options: UINT16 INT17

Usage

Butterworth Filter Characteristics

The Butterworth filter’s design is based on the Butterworth polynomial, which defines its transfer function. Key characteristics include:

  1. Maximally Flat Passband: The gain does not fluctuate and remains maximally flat, avoiding any distortion from ripples.

  2. Monotonic Decrease: Both in passband and stopband, the filter’s response decreases monotonically without oscillations.

  3. Pole Placement: The poles are placed on a circle in the z-plane and are evenly spaced, ensuring smooth transition characteristics.

Butterworth frequency response

Clustered Lookahead Implementation

To enable real-time FPGA operation at full clock rate, the filter uses the Clustered Lookahead technique. This transforms the recursive IIR structure to allow pipelined parallel processing.

First-order IIR block diagram

The standard first-order IIR equation:

$$ y[n] = b_0 x[n] + b_1 x[n-1] - a_1 y[n-1] $$

Is transformed using clustered lookahead to:

Clustered lookahead structure

$$ y[j] = b’_0 x[j] + b’_1 x[j-1] + b’_2 x[j-2] + b’_3 x[j-3] - a’_3 y[j-3] $$

Reference: A universal look-ahead algorithm for pipelining IIR filters

Coefficient Calculation

SciCompiler automatically calculates the filter coefficients using the internal filter calculator tool. The following Python code provides a reference implementation for offline simulation:

python 
  import numpy as np
from scipy import signal

N = 1               # Order of Filter
fs = 250*1e6        # Sampling frequency
fc = 0.2*1e6        # Cutoff frequency
Wn = fc/(fs/2)

b_z, a_z = signal.butter(N, Wn, btype='high')
print("Original", b_z, a_z)

an = [1, a_z[1]**3]
bn = [1, -a_z[1], a_z[1]**2]

bq = np.convolve(bn, b_z)
aq = an
print("Clustered", bq, aq)

Typical Applications

  • Simple signal filtering with smooth frequency response
  • DC blocking (high-pass mode)
  • Simple low-pass smoothing
  • Pre-filtering before more complex processing

Resources & Timing

  • Latency: 6 clock cycles