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Introduction

The MCA Short Signal block implements a complete digital pulse processing chain optimized for short signals and minimal FPGA area.

This block is ideal for applications where:

  • Pulses are short (up to ~512 samples shaping time)
  • FPGA resources are limited
  • Multiple channels are needed on small FPGAs
  • High count rate with short signals is required

The design uses fixed delay line sizes to minimize RAM and logic usage:

  • Trigger trapezoidal: 64 samples maximum
  • Energy trapezoidal: 512 samples maximum
  • Baseline restorer: 512 samples maximum

Unlike the full MCA HLS block which requires runtime HLS compilation, this block uses a pre-compiled VHD IP core that can be directly instantiated without Vitis HLS.

The block combines four processing stages:

  1. Fast Trapezoidal Trigger: Derivative-based trigger with short shaping times
  2. Slow Trapezoidal Shaper: Energy measurement with integrated deconvolution
  3. Baseline Restorer: Moving average with trigger-based hold
  4. Energy Sampler: Energy extraction with pile-up rejection (PUR)

Pin Description

DATA_IN Input 16 bit BIT VECTOR
16-bit input signal from the ADC. Connected to the detector/preamplifier output.
Default: Must be connected
POLARITY Input 1 bit BIT

Signal polarity selection.

  • 1: Positive polarity (signal increases on pulse)
  • 0: Negative polarity (signal inverted internally)
Default: 1
OFFSET Input 16 bit BIT VECTOR
16-bit digital offset added to the input signal. Used for DC level adjustment.
Default: 0
THRS Input 16 bit BIT VECTOR
16-bit trigger threshold. Applied to the derivative of the fast trapezoidal output. Higher values reduce noise triggers but may miss small pulses.
Default: 256
TRIG_K Input 16 bit BIT VECTOR
16-bit fast trapezoidal peaking time (rise time in clock cycles). Maximum value: 64 samples (limited by fixed delay line size). Shorter values give faster trigger response. Typical range: 4-32 samples.
Default: 6
TRIG_M Input 16 bit BIT VECTOR
16-bit fast trapezoidal total shaping parameter. Must be >= TRIG_K. Flat-top = TRIG_M - TRIG_K. Maximum value: 64 samples. Typical range: 8-64 samples.
Default: 8
TRAP_K Input 16 bit BIT VECTOR
16-bit slow trapezoidal peaking time (rise time in clock cycles). Maximum value: 512 samples (limited by fixed delay line size). Longer values provide better noise filtering. Typical range: 32-512 samples.
Default: 256
TRAP_M Input 16 bit BIT VECTOR
16-bit slow trapezoidal total shaping parameter. Must be >= TRAP_K. Flat-top = TRAP_M - TRAP_K. Maximum value: 512 samples.
Default: 266
DECONV_M Input 24 bit BIT VECTOR
24-bit deconvolution coefficient for pole-zero cancellation. Calculated as: M = int(256 / (exp(Ts/tau) - 1)) where Ts is sampling period and tau is preamplifier decay time. Shared between trigger and energy trapezoids.
Default: 31872
TRAP_GAIN Input 24 bit BIT VECTOR
24-bit gain coefficient for the trapezoidal outputs. Applied after deconvolution for amplitude scaling. Default 0x010000 = gain of 1.0.
Default: 65536
BL_LEN Input 4 bit BIT VECTOR
4-bit baseline averaging length exponent. Baseline window = 2^BL_LEN samples. Maximum: 2^9 = 512 samples (limited by fixed delay line). Example: BL_LEN=8 means 256-sample average.
Default: 8
BL_INIB Input 16 bit BIT VECTOR
16-bit baseline inhibit time in clock cycles. After each trigger, baseline calculation is frozen for this duration. Should be longer than pulse duration to prevent contamination.
Default: 4096
SAMPLE_POS Input 16 bit BIT VECTOR
16-bit energy sampling position in clock cycles after trigger. Optimal value: TRAP_K + (TRAP_M - TRAP_K) / 2. Should sample at the center of the flat-top region. Maximum: 512 samples.
Default: 264
RUN_CFG Input 1 bit BIT
EXT_TRIGGER Input 1 bit BIT
EXT_TRIGGER_SELECTOR Input 4 bit BIT VECTOR
PUR_MODE Input 4 bit BIT VECTOR

4-bit pile-up rejection mode selector.

  • 0: No PUR - all events accepted
  • 1: Simple PUR - reject if trigger during inhibit
  • 2+: State machine PUR - wait for clean window
Default: 0
PUR_INIB Input 16 bit BIT VECTOR
16-bit pile-up rejection inhibit time. Duration after energy sampling during which new triggers cause PUR flag. Used in PUR modes 1 and 2+.
Default: 0
CLK Input 1 bit BIT
System clock input. All internal operations are synchronous to the rising edge.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous reset. Clears all internal delay lines, accumulators, and state.
Default: Default Board Reset
ENERGY Output 32 bit BIT VECTOR
32-bit energy output. Valid when ENERGY_DV is high. Represents baseline-subtracted trapezoidal amplitude at sampling position.
ENERGY_STROBE Output 1 bit BIT
TRIGGER_OUT Output 1 bit BIT
BASELINE_HOLD Output 1 bit BIT
PUR Output 1 bit BIT
Pile-up rejection flag. HIGH when pile-up condition is detected. Use this to filter out pile-up events in software.
INPUT_SIGNAL Output 16 bit BIT VECTOR
16-bit delayed input signal output. Delayed by (TRIG_K + TRIG_M) samples for alignment monitoring.
TRIGGER_DELTA_MON Output 16 bit BIT VECTOR
16-bit trigger derivative monitor. Shows the difference signal used for threshold comparison. Useful for threshold optimization.
TRIGGER_TRAP_MON Output 16 bit BIT VECTOR
16-bit fast trapezoidal output monitor. Shows the output of the trigger trapezoidal filter.
TRAP_MON Output 32 bit BIT VECTOR
32-bit slow trapezoidal output monitor. Shows the raw energy trapezoidal output before baseline subtraction.
TRAP_BL_MON Output 32 bit BIT VECTOR
BL_MON Output 32 bit BIT VECTOR
32-bit baseline monitor. Shows the current baseline value calculated by the baseline restorer.
RUN(1) CFG(0) 1 bit

Run/Configure mode control.

  • 0: Configuration mode - parameters can be changed, processing reset
  • 1: Run mode - active processing
EXT_TRIG 1 bit
External trigger input. Used according to EXT_SEL mode selection.
EXT_SEL 4 bit

4-bit external trigger mode selector.

  • 0: Internal trigger only
  • 1: External trigger only
  • 2: Internal AND External
  • 3: Internal AND NOT External
ENERGY_DV 1 bit
Energy data valid strobe. HIGH for one clock cycle when a new energy value is available.
TRIGGER 1 bit
Trigger output pulse. HIGH for one clock cycle when a valid trigger is detected.
BL_HOLD 1 bit
Baseline hold indicator. HIGH when baseline calculation is inhibited (during pulse processing).
TRAP-BL_MON 32 bit
32-bit baseline-subtracted trapezoidal monitor. Shows (TRAP - BASELINE) for energy measurement verification.

Properties

Property window

Effective Number of Bits EffectiveNumberOfBits

Set the effective number of bits of the ADC board

Effective number of bits of the ADC. Used for polarity inversion calculation when POLARITY=0. Available values: 10, 12, 14, 16, default 14.

Default: 14

Options: 10 12 14 16

Usage

Signal Flow Diagram

MCA diagram

Resource Optimization

This block is specifically designed to minimize FPGA resource usage:

Resource MCA Short Signal MCA HLS (typical)
Trigger delay 64 samples fixed 128-16384 configurable
Energy delay 512 samples fixed 128-16384 configurable
Baseline delay 512 samples fixed 128-16384 configurable
HLS required No Yes
BRAM usage Low Medium-High

When to use this block:

  • Scintillator detectors with fast signals (< 4 µs shaping)
  • SiPM/PMT readout with short pulses
  • Multiple channel systems with limited FPGA resources
  • Applications where maximum shaping time is 512 samples

When to use MCA HLS instead:

  • HPGe detectors requiring long shaping times (> 512 samples)
  • High-resolution spectroscopy needing fine parameter tuning
  • Applications requiring timestamps

Processing Stages Detail

Stage 1: Fast Trapezoidal Trigger

The fast trapezoidal filter generates a trigger when a pulse is detected:

  • Maximum peaking time: 64 samples (TRIG_K)
  • Maximum flat-top: 64 samples (TRIG_M - TRIG_K)
  • Derivative-based threshold comparison

The trigger fires when:

  1. The derivative of the trapezoidal output exceeds THRS
  2. The derivative then crosses zero (peak detection)

Advantages:

  • No baseline calculation required for triggering
  • Immune to DC offset and baseline drift
  • Very fast response time

Stage 2: Slow Trapezoidal Shaper

Energy measurement filter with integrated deconvolution:

  • Maximum peaking time: 512 samples (TRAP_K)
  • Maximum flat-top: 512 samples (TRAP_M - TRAP_K)
  • Integrated pole-zero cancellation using DECONV_M
  • Output scaling with TRAP_GAIN

Trapezoidal Algorithm (Jordanov-Knoll):

$$ d^k[n] = x[n] - x[n-k] $$

$$ d^{k,l}[n] = d^k[n] - d^k[n-l] $$

$$ p[n] = p[n-1] + d^{k,l}[n] $$

$$ r[n] = p[n] + M \cdot d^{k,l}[n] $$

$$ s[n] = s[n-1] + r[n] $$

where:

  • $k$ = peaking time (TRAP_K)
  • $l$ = k + flat-top (TRAP_M)
  • $M$ = deconvolution coefficient (DECONV_M)

Stage 3: Baseline Restorer

Moving average baseline calculation:

$$ \text{baseline}[n] = \frac{1}{2^{\text{BL_LEN}}} \sum_{i=0}^{2^{\text{BL_LEN}}-1} \text{trap}[n-i] $$

  • Maximum averaging window: 512 samples
  • Baseline is held (frozen) for BL_INIB cycles after each trigger

Stage 4: Energy Sampler with Pile-Up Rejection

Samples energy at the flat-top and provides pile-up rejection (PUR):

$$ \text{energy} = \text{trap}[\text{trigger} + \text{SAMPLE_POS}] - \text{baseline} $$

PUR Modes:

PUR_MODE Description
0 No pile-up rejection - all events accepted
1 Simple PUR - reject if trigger during inhibit window
2+ State machine PUR - wait for clean measurement window

The PUR output indicates when pile-up is detected.

Calculating the Deconvolution Coefficient (DECONV_M)

The deconvolution coefficient removes the exponential decay from preamplifier signals:

$$ M = \frac{256}{e^{T_s / \tau} - 1} $$

where:

  • $T_s$ is the sampling period (1 / clock_frequency)
  • $\tau$ is the preamplifier decay time constant
  • The factor 256 comes from the internal 8-bit fixed-point scaling

Example calculation (Python):

python 
  import math

clock_freq = 125e6      # 125 MHz
tau = 50e-6             # 50 µs preamplifier decay time

Ts = 1.0 / clock_freq   # 8 ns
M = int(256 / (math.exp(Ts / tau) - 1))
# Result: M = 1599744 (0x186A00)

External Trigger Modes

The EXT_SEL input controls trigger source:

EXT_SEL Trigger Source
0 Internal trigger only
1 External trigger only (EXT_TRIG)
2 Internal AND External (coincidence)
3 Internal AND NOT External (anti-coincidence)

Saturation Protection

The block includes automatic saturation detection:

  • When input reaches 0xFFFF, processing is temporarily disabled
  • This prevents false triggers and energy measurements during saturation
  • Processing resumes automatically when saturation clears

Timing and Latency

  • Total processing latency: 17 clock cycles
  • Throughput: 1 sample per clock cycle (II=1)
  • Trigger to energy delay: Configurable via SAMPLE_POS

Typical Applications

  • Scintillator detectors (NaI, CsI, LaBr3, LYSO)
  • SiPM and PMT readout
  • Portable radiation monitors
  • Multi-channel gamma cameras
  • Resource-constrained FPGA designs